FUSB302B
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Table 33. STATUS0A
(Address: 3Ch; Reset Value: 0x0000_0000; Type: Read)
Bit #
Name R/W/C Size (Bits) Description
7:6 Reserved N/A 2 Do Not Use
5 SOFTFAIL R 1 1: All soft reset packets with retries have failed to get
a GoodCRC acknowledge. This status is cleared when
a START_TX, TXON or SEND_HARD_RESET is executed
4 RETRYFAIL R 1 1: All packet retries have failed to get a GoodCRC acknowledge.
This status is cleared when a START_TX, TXON or
SEND_HARD_RESET is executed
3:2 POWER3:POWER2 R 2 Internal power state when logic internals needs to control the
power state. POWER3 corresponds to PWR3 bit and POWER2
corresponds to PWR2 bit. The power state is the higher of both
PWR[3:0] and {POWER3, POWER2, PWR[1:0]} so that if one is
03 and the other is F then the internal power state is F
1 SOFTRST R 1 1: One of the packets received was a soft reset packet
0 HARDRST R 1 1: Hard Reset PD ordered set has been received
Table 34. STATUS1A
(Address: 3Dh; Reset Value: 0x0000_0000; Type: Read)
Bit #
Name R/W/C Size (Bits) Description
7:6 Reserved N/A 2 Do Not Use
5:3 TOGSS3,
TOGSS2,
TOGSS1
R 3 000: Toggle logic running (processor has previously written
TOGGLE=1)
001: Toggle functionality has settled to SRCon CC1
(STOP_SRC1 state)
010: Toggle functionality has settled to SRCon CC2
(STOP_SRC2 state)
101: Toggle functionality has settled to SNKon CC1
(STOP_SNK1 state)
110: Toggle functionality has settled to SNKon CC2
(STOP_SNK2 state)
111: Toggle functionality has detected AudioAccessory with vRa
on both CC1 and CC2 (settles to STOP_SRC1 state)
Otherwise: Not defined (do not interpret)
2 RXSOP2DB R 1 1: Indicates the last packet placed in the RxFIFO is type
SOP”_DEBUG (SOP double prime debug)
1 RXSOP1DB R 1 1: Indicates the last packet placed in the RxFIFO is type
SOP’_DEBUG (SOP prime debug)
0 RXSOP R 1 1: Indicates the last packet placed in the RxFIFO is type SOP
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Table 35. INTERRUPTA
(Address: 3Eh; Reset Value: 0x0000_0000; Type: Read/Clear)
Bit #
Name R/W/C Size (Bits) Description
7 I_OCP_TEMP R/C 1 1: Interrupt from either a OCP event on one of the VCONN
switches or an over-temperature event
6 I_TOGDONE R/C 1 1: Interrupt indicating the TOGGLE functionality was terminated
because a device was detected
5 I_SOFTFAIL R/C 1 1: Interrupt from automatic soft reset packets with retries have
failed
4 I_RETRYFAIL R/C 1 1: Interrupt from automatic packet retries have failed
3 I_HARDSENT R/C 1 1: Interrupt from successfully sending a hard reset ordered set
2 I_TXSENT R/C 1 1: Interrupt to alert that we sent a packet that was acknowledged
with a GoodCRC response packet
1 I_SOFTRST R/C 1 1: Received a soft reset packet
0 I_HARDRST R/C 1 1: Received a hard reset ordered set
Table 36. INTERRUPTB
(Address: 3Fh; Reset Value: 0x0000_0000; Type: Read/Clear)
Bit #
Name R/W/C Size (Bits) Description
7 Reserved N/A 6 Do Not Use
0 I_GCRCSENT R/C 1 1: Sent a GoodCRC acknowledge packet in response to
an incoming packet that has the correct CRC value
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27
Table 37. STATUS0
(Address: 40h; Reset Value: 0x0000_0000; Type: Read)
Bit #
Name R/W/C Size (Bits) Description
7 VBUSOK R 1 1: Interrupt occurs when VBUS transitions through vVBUSthr.
This bit typically is used to recognize port partner during
startup
6 ACTIVITY R 1 1: Transitions are detected on the active CC* line. This bit goes
high after a minimum of 3 CC transitions, and goes low with
no Transitions
0: Inactive
5 COMP R 1 1: Measured CC* input is higher than reference level driven from
the MDAC
0: Measured CC* input is lower than reference level driven
from the MDAC
4 CRC_CHK R 1 1: Indicates the last received packet had the correct CRC. This
bit remains set until the SOP of the next packet
0: Packet received for an enabled SOP* and CRC for the
enabled packet received was incorrect
3 ALERT R 1 1: Alert software an error condition has occurred. An alert is
caused by:
TX_FULL: the transmit FIFO is full
RX_FULL: the receive FIFO is full
See Status1 bits
2 WAKE R 1 1: Voltage on CC indicated a device attempting to attach
0: WAKE either not enabled (WAKE_EN=0) or no device
attached
1:0 BC_LVL[1:0] R 2 Current voltage status of the measured CC pin interpreted as host
current levels as follows:
00: < 200 mV
01: > 200 mV, < 660 mV
10: > 660 mV, < 1.23 V
11: > 1.23 V
Note the software must measure these at an appropriate time,
while there is no signaling activity on the selected CC line.
BC_LVL is only defined when Measure block is on which is when
register bits PWR[2]=1 and either MEAS_CC1=1 or MEAS_CC2=1
Table 38. STATUS1
(Address: 41h; Reset Value: 0x0010_1000; Type: Read)
Bit #
Name R/W/C Size (Bits) Description
7 RXSOP2 R 1 1: Indicates the last packet placed in the RxFIFO is type SOP”
(SOP double prime)
6 RXSOP1 R 1 1: Indicates the last packet placed in the RxFIFO is type SOP’
(SOP prime)
5 RX_EMPTY R 1 1: The receive FIFO is empty
4 RX_FULL R 1 1: The receive FIFO is full
3 TX_EMPTY R 1 1: The transmit FIFO is empty
2 TX_FULL R 1 1: The transmit FIFO is full
1 OVRTEMP R 1 1: Temperature of the device is too high
0 OCP R 1 1: Indicates an over-current or short condition has occurred on
the VCONN switch

FUSB302BUCX

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC USB TYPE C CTLR PROGR 9WLCSP
Lifecycle:
New from this manufacturer.
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