ZL30410 Data Sheet
List of Tables
4
Zarlink Semiconductor Inc.
Table 1 - Operating Modes and States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2 - Filter Characteristic Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3 - Reference Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ZL30410 Data Sheet
5
Zarlink Semiconductor Inc.
1.0 Change Summary
Changes from March 2006 Issue to November 2006 Issue. Page, section, figure and table numbers refer to this
current issue.
Changes from February 2006 Issue to March 2006 Issue. Page, section, figure and table numbers refer to this
current issue.
2.0 ZL30410 Pinout
2.1 Pin Connections
Figure 2 - Pin Connections for 80-pin LQFP package
Page Item Change
28 Figure 18 Adjusted drawing.
Page Item Change
1 Ordering Information Box Updated Ordering Information.
ZL30410
40
42444648505254565860
22
24
26
28
30
34
36
38
32
62
80
78
76
74
72
68
66
64
70
2018161412108642
Tdi
Tcl k
Tms
Tdo
NC
GND
PRI
SEC
E3/DS3
E3DS3/OC3
C155P
C155N
VDD
AVDD
GND
IC
GND
NC
Trst
NC
MS1
NC
C4o
C8o
C16o
F16o
GND
VDD
FCS
NC
F0o
C2o
IC
NC
NC
MS2
GND
NC
F8o
SECOR
OE
NC
RESET
NC
IC
IC
IC
GND
IC
IC
NC
IC
VDD
IC
IC
IC
IC
NC
C1.5o
C19o
RefSel
RefAlign
VDD
NC
C20i
C34/C44
GND
VDD
HOLDOVER
NC
LOCK
NC
IC
PRIOR
GND
IC
C6o
IC
NC
IC
ZL30410 Data Sheet
6
Zarlink Semiconductor Inc.
.
Pin Description
Pin # Name Description
1ICInternal Connection. Leave unconnected.
2-5 NC No internal bonding Connection. Leave unconnected.
6GNDGround. Negative power supply.
7, 8 NC No internal bonding Connection. Leave unconnected.
9FCSFilter Characteristic Select (Input). In Hardware Control, FCS selects the
filtering characteristics of the ZL30410. Set this pin high to have a loop filter
corner frequency of 6 Hz and limit the phase slope to 41 ns per 1.326 ms. Set
this pin low to have corner frequency of 12 Hz with no phase slope limiting
imposed. This pin is internally pulled down to GND.
10 VDD Positive Power Supply
11 GND Ground
12 F16o
Frame Pulse ST-BUS 8.192 Mbps (CMOS tristate output). This is an 8 kHz,
61 ns wide, active low framing pulse, which marks beginning of a ST-BUS
frame. This frame pulse is typically used for ST-BUS operation at 8.192 Mbps.
13 C16o
Clock 16.384 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mbps.
14 C8o Clock 8.192 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 8.192 Mbps.
15 C4o
Clock 4.096 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mbps.
16 C2o Clock 2.048 MHz (CMOS tristate output). This clock is used for ST-BUS
operation at 2.048 Mbps.
17 F0o
Frame Pulse ST-BUS 2.048 Mbps (CMOS tristate output). This is an 8 kHz,
244 ns, active low framing pulse, which marks the beginning of a ST-BUS
frame. This is typically used for ST-BUS operation at 2.048 Mbps and
4.096 Mbps.
18 MS1 Mode Select 1 (Input). The MS1 and MS2 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 16 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
19 MS2 Mode Select 2 (Input). The MS2 and MS1 pins select the ZL30410 mode of
operation (Normal, Holdover or Free-run), see Table 1 on page 16 for details.
The logic level at this input is sampled by the rising edge of the F8o frame
pulse.
20 F8o Frame Pulse ST-BUS/GCI 8.192 Mbps (CMOS tristate output). This is an 8
kHz, 122 ns, active high framing pulse, which marks the beginning of a
ST-BUS/GCI frame. This is typically used for ST-BUS/GCI operation at
8.192 Mbps. See Figure 15 for details.

ZL30410QCG1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Phase Locked Loops - PLL
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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