ZL30410QCG1 Datasheet ZL30410QCG1 | P7-P9

ZL30410 Data Sheet

Zarlink Semiconductor Inc.

21 E3DS3/OC3 E3DS3 or OC3 Selection (Input). In Hardware Control, a logic low on this pin

enables the C155P/N outputs (pin 30 and pin 31) and sets the C34/C44 output

(pin 53) to provide C8 or C11 clocks. Logic high at this input disables the C155

clock outputs (high impedance) and sets C34/C44 output to provide C34 and

C44 clocks.

22 E3/DS3

E3 or DS3 Selection (Input). In Hardware Control, when the E3DS3/OC3 pin

is set high, logic low on E3/DS3

pin selects a 44.736 MHz clock on C34/C44

output and logic high selects 34.368 MHz clock. When E3DS3/OC3

pin is set

low, logic low on E3/DS3

pin selects 11.184 MHz clock on C34/C44 output and

logic high selects 8.592 MHz clock.

23 SEC Secondary Reference (Input). This input is used as a secondary reference

source for synchronization. The ZL30410 can synchronize to the falling edge

of the 8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the

19.44 MHz clock. In Hardware Control, selection of the input reference is

based upon the RefSel control input. This pin is internally pulled up to VDD.

24 PRI Primary Reference (Input). This input is used as a primary reference source

for synchronization. The ZL30410 can synchronize to the falling edge of the

8 kHz, 1.544 MHz or 2.048 MHz clocks and the rising edge of the 19.44 MHz

clock. In Hardware Control, selection of the input reference is based upon the

RefSel control input. This pin is internally pulled up to VDD.

25 GND Ground

26 IC Internal Connection. Leave unconnected.

27 GND Ground

28 AVDD Positive Analog Power Supply. Connect this pin to VDD.

29 VDD Positive Power Supply.

C155N

C155P

Clock 155.52 MHz (LVDS output). Differential outputs for the 155.52 MHz

clock. These outputs are enabled by applying logic low to E3DS3/OC3

input or

they can be disabled by applying logic high. In the disabled state the LVDS

outputs are internally terminated with an integrated 100 Ω resistor (two 50Ω

resistors connected in series). The middle point of these resistors is internally

biased from a 1.25 V LVDS bias source.

32 GND Ground

33 NC No internal bonding Connection. Leave unconnected.

34 Tdo IEEE1149.1a Test Data Output (CMOS output). JTAG serial data is output on

this pin on the falling edge of Tclk clock. If not used, this pin should be left

unconnected.

35 Tms IEEE1149.1a Test Mode Selection (3.3 V input). JTAG signal that controls the

state transition on the TAP controller. This pin is internally pulled up to VDD. If

not used, this pin should be left unconnected.

Pin Description (continued)

Pin # Name Description

ZL30410 Data Sheet

Zarlink Semiconductor Inc.

36 Tclk IEEE1149.1a Test Clock Signal (5 V tolerant input). Input clock for the JTAG

test logic. If not used, this pin should be pulled up to VDD.

37 Trst

IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG

TAP controller. This pin should be pulsed low on power-up to ensure that the

device is in the normal functional state. This pin is internally pulled up to VDD.

If this pin is not used then it should be connected to GND.

38 Tdi IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test

instructions and data. This pin is internally pulled up to VDD. If not used, this

pin should be left unconnected.

39 NC No internal bonding Connection. Leave unconnected.

40 NC No internal bonding Connection. Leave unconnected.

41 PRIOR Primary Reference Out of Range (Output). Logic high at this pin indicates

that the Primary Reference is off the PLL centre frequency by more than

±12 ppm. See PRIOR pin description in Section 4.2 on page 17 for details.

42 C1.5o Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz

DS1 rate clock.

43 C6o Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz

DS2 rate clock.

44 IC Internal Connection. Connect this pin to Ground.

45 GND Ground

46 C19o Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz

clock.

47 RefSel Reference Source Select (Input). A logic low selects the PRI (primary)

reference source as the input reference signal and logic high selects the SEC

(secondary) input. The logic level at this input is sampled at the rising edge of

F8o. This pin is internally pulled down to GND.

48 RefAlign

Reference Alignment (Input). In Hardware Control pulling this pin low for

250 µs initiates phase realignment between the input reference and the

generated output clocks. See Section 3.2.4 on page 11 for details. This pin

should never be tied low permanently. Internally this pin is pulled down to

GND.

49 VDD Positive Power Supply

50 NC No internal bonding Connection. Leave unconnected.

51 C20i Clock 20 MHz (5 V tolerant input). This pin is the input for the 20 MHz Master

Clock Oscillator. The clock oscillator should be connected directly (not AC

coupled) to the C20i input and it must supply clock with duty cycle that is not

worse than 40/60%.

52 GND Digital Ground

Pin Description (continued)

Pin # Name Description

ZL30410 Data Sheet

Zarlink Semiconductor Inc.

53 C34/C44 Clock 34.368 MHz / clock 44.736 MHz (CMOS Output). This clock is

programmable to be either 34.368 MHz (for E3 applications) or 44.736 MHz

(for DS3 applications) when E3DS3/OC3

is high, or to be either 8.592 MHz or

11.184 MHz when E3DS3/OC3

is low. See description of E3DS3/OC3 and

E3/DS3

inputs for details.

54 VDD Positive Power Supply

55 HOLDOVER Holdover Indicator (CMOS output). Logic high at this output indicates that the

device is in Holdover mode.

56 NC No internal bonding Connection. Leave unconnected.

57 LOCK Lock Indicator (CMOS output). Logic high at this output indicates that

ZL30410 is locked to the input reference. See LOCK indicator description in

Section 3.2.3, “Lock Indicator (LOCK),” on page 11.

58 NC No internal bonding Connection. Leave unconnected.

59 IC Internal Connection. Connect to logic high.

60 IC Internal Connection. Connect to ground.

61 SECOR Secondary Reference Out of Range (Output). Logic high at this pin indicates

that the Secondary Reference is off the PLL centre frequency by more than

±12 ppm. See SECOR (PRIOR) pin description in Section 4.2 on page 17 for

details.

62 OE Output Enable (Input). Logic high on this input enables C19, F16

, C16, C8,

C6, C4

, C2, C1.5, F8 and F0 signals. Pulling this input low will force the output

clocks pins into a high impedance state.

63 NC No internal bonding Connection. Leave unconnected.

64 RESET

RESET (5V tolerant input). The ZL30410 must be reset after power-up in order

to set internal functional blocks into a default state. The internal reset is

performed by forcing RESET

pin low for a minimum of 1 µs after the C20

Master Clock is applied to pin C20i. This operation forces the ZL30410 internal

state machine into a RESET state for a duration of 625 µs.

65 NC No internal bonding Connection. Leave unconnected.

66-69 IC Internal connection. Connect these pins to logic high.

70 GND Ground

71, 72 IC Internal Connection (Input). Connect these pins to ground.

73 VDD Positive Power Supply

74 - 77 IC Internal connection. Connect these pins to logic high.

78, 79 NC No internal bonding Connection. Leave unconnected.

80 IC Internal Connection (Input). Connect this pin to ground.

Pin Description (continued)

Pin # Name Description

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39

ZL30410QCG1

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Buy ZL30410QCG1

Manufacturer:

Microchip / Microsemi

Description:

Phase Locked Loops - PLL

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