NCP81080DR2G

NCP81080
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10
threshold. The typical VHB UVLO rising threshold is 4.4 V
with 0.35 V hysteresis.
At power up, when the supply voltage ramps up to set
VDD and crosses the UVLO thresholds, users must take
into account a 20 ms delay before the output drivers can
react to a logic input. The 20 ms delay applies to both
High−side and Low−side drivers. Figure 4 only shows the
delay for the low−side channel.
Input Stage
The input stage of the NCP81080 is TTL compatible. The
logic rising threshold level is 2.0 V and the logic falling
threshold is 0.8 V.
Cross−Conduction Protection
The NCP81080’s inputs HI & LI are controlled
independently. In order to prevent the power stage
MOSFETs from turning on at the same time an internal logic
circuit is implemented to monitor the state of HI & LI. If both
input signals are high at the same time, the output signals HO
& LO are forced low. (See Timing Diagram)
UVLO Crossing
When VDD & VHB cross their respective UVLO
thresholds if HI and LI were already set the NCP81080 will
keep HO pulled Low until it detects a rising edge on HI,
however LO will follow LI allowing the Low−Side FET to
turn on. (Refer to Figure 4)
Layout Guidelines
Gate drivers experience high di/dt during the switching
transitions. So, the inductance at the gate drive traces must
be minimized to avoid excessive ringing on the switch node.
Gate drive traces should be kept as short and wide (>20 mil)
as practical. The input capacitor must be placed as close as
possible to the IC. Connect the VSS pin of the NCP81080 as
close as possible to the source of the lower MOSFET. The
use of vias is highly desirable to maximize thermal
conduction away from driver.
NCP81080
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11
PACKAGE DIMENSIONS
DFN8 2x2
CASE 506AA
ISSUE F
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
2.30
0.50
0.50
8X
DIMENSIONS: MILLIMETERS
0.30
PITCH
8X
1
PACKAGE
OUTLINE
RECOMMENDED
0.90
1.30
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
D
E
B
C0.10
PIN ONE
2X
REFERENCE
2X
TOP VIEW
SIDE VIEW
BOTTOM VIEW
A
L
(A3)
D2
E2
C
C0.10
C0.10
C0.08
NOTE 4
A1
SEATING
PLANE
e/2
e
8X
K
NOTE 3
b
8X
0.10 C
0.05 C
A
BB
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.20 0.30
D 2.00 BSC
D2 1.10 1.30
E 2.00 BSC
E2 0.70 0.90
e 0.50 BSC
K
L 0.25 0.35
1
4
8
5
L1
DETAIL A
L
OPTIONAL
CONSTRUCTIONS
L
DETAIL B
DETAIL A
L1 −− 0.10
0.30 REF
DETAIL B
MOLD CMPDEXPOSED Cu
ALTERNATE
CONSTRUCTIONS
A1
A3
NCP81080
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12
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z
S
X
S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
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NCP81080DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers LOW-COST HIGH VLTG GATE DRIVER
Lifecycle:
New from this manufacturer.
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