NCP81080DR2G

NCP81080
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7
TYPICAL CHARACTERISTICS
Figure 7. Propagation Delays vs. Supply
Voltage
Figure 8. Propagation Delays vs. Temperature
SUPPLY VOLTAGE (V) TEMPERATURE (°C)
24201816121086
0
10
20
30
40
50
60
1251007550250−25−50
0
10
20
30
40
50
60
70
Figure 9. Input Thresholds vs. Supply Voltage Figure 10. Input Thresholds vs. Temperature
SUPPLY VOLTAGE (V) TEMPERATURE (°C)
0
0.2
0.4
0.8
1.0
1.2
1.6
1.8
0
0.2
0.6
0.8
1.0
1.4
1.8
2.0
Figure 11. Supply Current vs. Frequency Figure 12. Diode Current vs. Diode Voltage
FREQUENCY (kHz) DIODE VOLTAGE (V)
92572562542532522512525
0
2
4
8
10
12
16
18
1.91.71.31.10.70.50.30.1
0.001
0.01
0.1
1
10
100
PROPAGATION DELAYS (nS)
PROPAGATION DELAYS (nS)
INPUT THRESHOLDS (V)
INPUT THRESHOLDS (V)
SUPPLY CURRENT (mA)
DIODE CURRENT (mA)
Ihb
Idd
Falling
Rising
0.6
1.4
Falling
Rising
Falling
Rising
Falling
Rising
14 22 150
1251007550250−25−50 150
0.4
1.2
1.6
242018161210861422
525 825 1025
6
14
0.9 1.5 2.1
NCP81080
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8
TYPICAL CHARACTERISTICS
Figure 13. Quiescent Current vs. Supply
Voltage
Figure 14. Quiescent Current vs. Supply
Voltage
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
22181614121086
0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Figure 15. Quiescent Current vs. Supply
Voltage
Figure 16. Quiescent Current vs. Supply
Voltage
SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
0
0.5
1.0
1.5
2.0
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
20 24 221816141210862024
221816141210862024 221816141210862024
2.5
HI = 1
LI = 0
Ihb
Idd
HI = 0
LI = 0
Ihb
Idd
HI = 1
LI = 1
Ihb
Idd
HI = 0
LI = 1
Ihb
Idd
NCP81080
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9
APPLICATION INFORMATION
The NCP81080 is a high performance dual MOSFET gate
driver optimized to drive half bridge N−Channel MOSFETs.
A high and a Low input signals are all that is required to
properly drive the power stage. The input signals are
independently controlled and monitored by an anti−cross
conduction circuit in order to prevent current shoot through.
The NCP81080 has UVLO protections for the high−side and
low−side drivers forcing the outputs low if the bias supplies
drop below the specified UVLO thresholds. The NCP81080
also features an on−chip high voltage bootstrap diode which
reduces the external component count. The NCP81080 has
a fixed internal dead−time of 135 ns.
Driver Supply Voltage
As a general rule of thumb the local bypass should be 20
times the bootstrap capacitor. It is recommended to use a
4.7 mF bypass capacitor on VDD to VSS. The bootstrap
capacitor is recharged on a cycle by cycle basis through the
bootstrap diode from the VDD bypass capacitor. The
charging cycle involves bursts in peak currents that require
careful considerations by keeping a tight layout and short
loops to avoid reliability issues.
If for any reason the application requires the VDD voltage
to discharge to ground at rapid rates (3 + V/ms) the user is
required to add an external diode between the supply voltage
and the bypass capacitor.
Figure 17. VDD Diode
NCP81080
VSS
12V
VDD
Low−Side Driver
The low side driver is designed to drive low RDS
ON
N−channel MOSFETs. The typical output resistances for the
driver are 7.5 ohms for sourcing and 3.1 ohms for sinking
gate current. The bias to the low side driver is internally
connected to the VDD supply and VSS. When the driver is
enabled, the drivers output is in phase with LI. When the
NCP81080 is disabled, the low side gate is held low.
High−Side Driver
The high side driver is designed to drive a floating low
RDS
ON
N−channel MOSFET. The output resistances for the
driver are 7.1 ohms for sourcing and 3.1 ohms for sinking
gate current. The bias voltage for the high side driver is
realized by an external bootstrap supply circuit which is
connected between the HB and HS Pins.
The peak diode current that the part can handle is 8 A. It
is required to add an external limiting resistor in series with
the bootstrap capacitor to prevent damaging the internal
diode.
At power−up, the HS Pin is at ground, the bootstrap
capacitor will charge up to VDD through the internal diode.
The designer must factor in at least 3 time constants (RC)
plus the internal UVLO delays (20 ms typical) before the
output can react to a logic input (Refer to Figure 4). If for any
reason the voltage across the bootstrap capacitor drops
below UVLO, it is required to charge the capacitor back up
to VDD while accounting for 3 time constants and the 20 ms
UVLO delay before the High−Side channel can react to an
HI input.
When the HI pin goes high, the high side driver will begin
to turn the high side MOSFET ON by pulling charge out of
the bootstrap capacitor. As the external MOSFET turns ON,
the HS Pin will rise up to VIN, forcing the HB Pin to VIN
+ V
BstCap
which is enough gate to source voltage to hold the
switch On. To complete the cycle, the MOSFET is switched
OFF by pulling the gate down to the voltage at the HS Pin.
When the low side MOSFET turns On, the HS Pin is pulled
to ground. This allows the bootstrap capacitor to charge back
up to VDD. The high−side drivers output is in phase with
the HI input. When the driver is disabled, the high side gate
is held low.
Table 6. TYPICAL EXTERNAL CURRENT LIMITING
RESISTOR VALUES
VDD (V)
Bootstrap Capacitor
(mF)
External Resistor
(ohms)
12 0.1 2
12 1 3
18 0.1 3
NCP81080
HB
HS
Resistor
Bootstrap
Capacitor
Figure 18. External Current Limiting Resistor
UVLO (Under Voltage Lockout)
The bias supplies of the high−side and low−side drivers
have UVLO protection. The VDD UVLO disables both
drivers when the VDD voltage crosses the specified
threshold. The typical rising threshold is 4.4 V with 0.4 V
hysteresis. The VHB UVLO disables only the high−side
driver when the VHB to VHS is below the specified

NCP81080DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Gate Drivers LOW-COST HIGH VLTG GATE DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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