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AD640BPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD640
REV. D–12–
can be adjusted by adding or subtracting a small current to the
output. Since the slope current is 1 mA/decade, a 50 µA incre-
ment will move the intercept by 1 dB. Note that any error in
this current will invalidate the calibration of the AD640. For
example, if one of the 5 V supplies were used with a resistor to
generate the current to reposition the intercept by 20 dB, a
±10% variation in this supply will cause a ±2 dB error in the
absolute calibration. Of course, slope calibration is unaffected.
Source Resistance and Input Offset
The bias currents at the signal inputs (Pins 1 and 20) are typi-
cally 7 µA. These flow in the source resistances and generate
input offset voltages which may limit the dynamic range because
the AD640 is direct coupled and an offset is indistinguishable
from a signal. It is good practice to keep the source resistances
as low as possible and to equalize the resistance seen at each
input. For example, if the source resistance to Pin 20 is 100 Ω, a
compensating resistor of 100 Ω should be placed in series with
Pin l. The residual offset is then due to the bias current offset,
which is typically under 1 µA, causing an extra offset uncertainty
of 100 µV in this example. For a single AD640 this will rarely be
troublesome, but in some applications it may need to be nulled
out, along with the internal voltage offset component. This may
be achieved by adding an adjustable voltage of up to ±250 µV at
the unused input. (Pins l and 20 may be interchanged with no
change in function.)
In most applications there will be no need to use any offset
adjustment. However, a general offset trimming circuit is shown
in Figure 25. R
S
is the source resistance of the signal. Note: 50 Ω
rf sources may include a blocking capacitor and have no dc path to
ground, or may be transformer coupled and have a near zero resis-
tance to ground. Determine whether the source resistance is zero,
25 Ω or 50 Ω (with the generator terminated in 50 Ω) to find
the correct value of bias compensating resistor, R
B
, which
should optimally be equal to R
S
, unless R
S
= 0, in which case
use R
B
= 5 Ω. The value of R
OS
should be set to 20,000 R
B
to
provide a ±250 µV trim range. To null the offset, set the source
voltage to zero and use a DVM to observe the logarithmic out-
put voltage. Recall that the LOG OUT current of the AD640
exhibits an absolute value response to the input voltage, so the offset
potentiometer is adjusted to the point where the logarithmic output
“turns around” (reaches a local maximum or minimum).
–5V
(SOURCE RESISTANCE
OF TERMINATED
GENERATOR)
R
B
19
20
12
AD640
R
OS
R
S
+5V
20kV
Figure 25. Optional Input Offset Voltage Nulling Circuit;
See Text for Component Values
At high frequencies it may be desirable to insert a coupling
capacitor and use a choke between Pin 20 and ground, when
Pin 1 should be taken directly to ground. Alternatively, trans-
former coupling may be used. In these cases, there is no added
offset due to bias currents. When using two dc coupled AD640s
(overall gain 100,000), it is impractical to maintain a sufficiently
low offset voltage using a manual nulling scheme. The section
CASCADED OPERATION explains how the offset can be
automatically nulled to submicrovolt levels by the use of a nega-
tive feedback network.
Using Higher Supply Voltages
The AD640 is calibrated using ±5 V supplies. Scaling is very
insensitive to the supply voltages (see dc SPECIFICATIONS)
and higher supply voltages will not directly cause significant
errors. However, the AD640 power dissipation must be kept
below 500 mW in the interest of reliability and long-term stabil-
ity. When using well regulated supply voltages above ±6 V, the
decoupling resistors shown in the application schematics can be
increased to maintain ±5 V at the IC. The resistor values are
calculated using the specified maximum of 15 mA current into
the +V
S
terminal (Pin 12) and a maximum of 60 mA into the
–V
S
terminal (Pin 7). For example, when using ±9 V supplies, a
resistor of (9 V–5 V)/15 mA, about 261 Ω, should be included in
the +V
S
lead to each AD640, and (9 V–5 V)/60 mA, about 64.9 Ω,
in each –V
S
lead. Of course, asymmetric supplies may be dealt
with in a similar way.
Using the Attenuator
In applications where the signal amplitude is sufficient, the on-
chip attenuator should be used because it provides a tempera-
ture independent dynamic range (compare Figures 18 and 19).
Figure 26 shows this attenuator in more detail. R1 is a thin-film
resistor of nominally 270 Ω and low temperature coefficient
(TC). It is trimmed to calibrate the intercept to 10 mV dc (or
–24 dBm for sinusoidal inputs), that is, to an attenuation of
nominally 20 dBs at 27°C. R2 has a nominal value of 30 Ω and
has a high positive TC, such that the overall attenuation factor
is 0.33%/°C at 27°C. This results in a transmission factor that is
proportional to absolute temperature, or PTAT. (See Intercept
Stabilization for further explanation.) To improve the accuracy
of the attenuator, the ATN COM nodes are bonded to both
Pin 3 and Pin 4. These should be connected directly to the “SIG-
NAL LOW” of the source (for example, to the grounded side of
the signal connector, as shown in Figure 32) not to an arbitrary
point on the ground plane.
43215
17181920 16
ATN
COM
SIG
–IN
SIG
+IN
ATN
COM
ATN
LO
ATN
IN
R3
R4
R1
R2
ATN
OUT
FIRST
AMPLIFIER
INPUT
AD640
Figure 26. Details of the Input Attenuator
R4 is identical to R2, and in shunt with R3 (270 Ω thin film)
forms a 27 Ω resistor with the same TC as the output resistance
of the attenuator. By connecting Pin 1 to ATN LOW (Pin 2)
this resistance minimizes the offset caused by bias currents. The
offset nulling scheme shown in Figure 25 may still be used, with
the external resistor R
B
omitted and R
OS
= 500 kΩ. Offset sta-
bility is improved because the compensating voltage introduced
at Pin 20 is now PTAT. Drifts of under 1 µV/°C (referred to
Pins 1 and 20) can be maintained using the attenuator.
AD640
REV. D –13–
It may occasionally be desirable to attenuate the signal even
further. For example, the source may have a full-scale value of
±10 V, and since the basic range of the AD640 extends only to
±200 mV dc, an attenuation factor of ×50 might be chosen.
This may be achieved either by using an independent external
attenuator or more simply by adding a resistor in series with
ATN IN (Pin 5). In the latter case the resistor must be trimmed
to calibrate the intercept, since the input resistance at Pin 5 is
not guaranteed. A fixed resistor of 1 kΩ in series with a 500 Ω
variable resistor calibrate to an intercept of 50 mV (or –26 dBV)
for dc or square wave inputs and provide a ±10 V input range.
The intercept stability will be degraded to about 0.003 dB/°C.
OPERATION OF CASCADED AD640S
Frequently, the dynamic range of the input will be 50 dB or
more. AD640s can be cascaded, as shown in Figure 27. The
balanced signal output from U1 becomes the input to U2. Re-
sistors are included in series with each LOG OUT pin and
capacitors C1 and C2 are placed directly between Pins 13 and 14
to provide a local path for the RF current at these output pairs.
C1 through C3 are chosen to provide the required low-pass
corner in conjunction with the load R
L
. Board layout and
grounding disciplines are critically important at the high gain
(X100,000) and bandwidth (~150 MHz) of this system.
The intercept voltage is calculated as follows. First, note that if
its LOG OUT is disconnected, U1 simply inserts 50 dB of
gain ahead of U2. This would lower the intercept by 50 dB, to
–110 dBV for square wave calibration. With the LOG OUT of
U1 added in, there is a finite zero signal current which slightly
shifts the intercept. With the intercept temperature compensa-
tion on U1 disabled this zero signal output is –270 µA (see DC
SPECIFICATIONS) equivalent to a 5.4 dB upward shift in the
intercept, since the slope is 50 µA/dB. Thus, the intercept is at
–104.6 dBV (–88.6 dBm for 50 Ω sine calibration). ITC may be
disabled by grounding Pin 8 of either U1 or U2.
Cascaded AD640s can be used in dc applications, but input
offset voltage will limit the dynamic range. The dc intercept is
6 µV. The offset should not be confused with the intercept, which is
found by extrapolating the transfer function from its central “log
linear” region. This can be understood by referring to Equation
(1) and noting that an input offset is simply additive to the value
of V
IN
in the numerator of the logarithmic argument; it does not
affect the denominator (or intercept) V
X
. In dc coupled applica-
tions of wide dynamic range, special precautions must be taken
to null the input offset and minimize drift due to input bias
offset. It is recommended that the input attenuator be used,
providing a practical input range of –74 dBV (±200 µV dc) to
+6 dBV (±2 V dc) when nulled using the adjustment circuit
shown in Figure 25.
Eliminating the Effect of First Stage Offset
Usually, the input signal will be sinusoidal and U1 and U2 can
be ac coupled. Figure 28a shows a low resistance choke at the
input of U2 which shorts the dc output of U1 while preserving
the hf response. Coupling capacitors may be inserted (Fig-
ure 28b) in which case two chokes are used to provide bias
paths for U2. These chokes must exhibit high impedance over
the operating frequency range.
20
1
U2
U1
11
10
20
1
U2
U1
11
10
a. b.
Figure 28. Two Methods for AC-Coupling AD640s
Alternatively, the input offset can be nulled by a negative feed-
back network from the SIG OUT nodes of U2 to the SIG IN
nodes of U1, as shown in Figure 29. The low-pass response of
the feedback path transforms to a closed-loop high-pass re-
sponse. The high gain (×100,000) of the signal path results in a
commensurate reduction in the effective time constant of this
network. For example, to achieve a high-pass corner of 100 kHz,
the low-pass corner must be at 1 Hz.
In fact, it is somewhat more complicated than this. When the ac
input sufficiently exceeds that of the offset, the feedback be-
comes ineffective and the response becomes essentially dc
coupled. Even for quite modest inputs the last stage will be
limiting and the output (Pins 10 and 11) of U2 will be a square
wave of about ±180 mV amplitude, dwelling approximately
equal times at its two limit values, and thus having a net average
value near zero. Only when the input is very small does the high-
pass behavior of this nulling loop become apparent. Consequently,
the low-pass time constant can usually be reduced considerably
without serious performance degradation.
The resistor values are chosen such that the dc feedback is ade-
quate to null the worst case input offset, say, 500 µV. There
R
L
= 50V
C3
1mA/DECADE
15
131416
19
18
17 11
1220
6 8753 4 1091
2
SIG
+IN
ATN
OUT
CKT
COM
RG1 RG0 RG2 LOG
OUT
LOG
COM
+V
S
SIG
+OUT
SIG
–IN
ATN
LO
ATN
COM
BL1 BL2ITC
–V
S
SIG
–OUT
1kV 1kV
ATN
COM
ATN
IN
U1 AD640
NC
4.7V
+5V
–5V
R1
R2
NC
NC
15
131416
19
18
17 11
1220
6 8753 4 1091
2
SIG
+IN
ATN
OUT
CKT
COM
RG1 RG0 RG2 LOG
OUT
LOG
COM
+V
S
SIG
+OUT
SIG
–IN
ATN
LO
ATN
COM
BL1 BL2ITC
–V
S
SIG
–OUT
1kV 1kV
ATN
COM
ATN
IN
U2 AD640
C1
10V 10V
C2
10V 10V
OUTPUT
–50mV/DECADE
4.7V
DENOTES A CONNECTION TO THE GROUND PLANE;
OBSERVE COMMON CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE 0.1mF CERAMIC.
SEE TEXT FOR VALUES OF NUMBERED COMPONENTS.
SIGNAL
INPUT
NC = NO CONNECT
Figure 27. Basic Connections for Cascaded AD640s
AD640
REV. D–14–
15 13141619 18 17 1112
20
6
8
753
4 1091
2
SIG
+IN
ATN
OUT
CKT
COM
RG1 RG0 RG2 LOG
OUT
LOG
COM
+V
S
SIG
+OUT
SIG
–IN
ATN
LO
ATN
COM
BL1 BL2ITC
–V
S
SIG
–OUT
1kV 1kV
ATN
COM
ATN
IN
U1 AD640
NC
R1
R2
NC
NC
15 13141619 18 17 1112
20
6
8
753
4 1091
2
SIG
+IN
ATN
OUT
CKT
COM
RG1 RG0 RG2 LOG
OUT
LOG
COM
+V
S
SIG
+OUT
SIG
–IN
ATN
LO
ATN
COM
BL1 BL2ITC
–V
S
SIG
–OUT
1kV 1kV
ATN
COM
ATN
IN
U2 AD640
C1
47pF
R3
100V
68V
C2
47pF
R4
100V
18V
L1
(SEE
TEXT)
18V
–6V
+6V
68V
–6V
4.7V
U3
AD844
LOG
OUTPUT
+50mV/dB
(LO)
+6V
4.7V
DENOTES A CONNECTION TO THE GROUND PLANE;
OBSERVE COMMON CONNECTIONS WHERE SHOWN.
ALL UNMARKED CAPACITORS ARE 0.1mF CERAMIC.
SEE TEXT FOR VALUES OF NUMBERED COMPONENTS.
SIGNAL
INPUT
R13
1.13kV
(SEE TEXT)
NC = NO CONNECT
Figure 30. Complete 70 dB Dynamic Range Converter for 50 MHz–150 MHz Operation
must be some resistance at Pins 1 and 20 across which the offset
compensation voltage is developed. The values shown in the
figure assume that we wish to terminate a 50 Ω source at Pin 20.
The 50 Ω resistor at Pin 1 is essential, both to minimize offsets
due to bias current mismatch and because the outputs at Pins
10 and 11 can only swing negatively (from ground to –180 mV)
whereas we need to cater for input offsets of either polarity.
For a sine input of 1 µV amplitude (–120 dBV) and in the
absence of offset, the differential voltage at Pins 10 and 11 of
U2 would be almost sinusoidal but 100,000 times larger, or
100 mV. The last limiter in U2 would be entering saturation. A
1 µV input offset added to this signal would put the last limiter
well into saturation, and its output would then have a different
average value, which is extracted by the low-pass network and
delivered back to the input. For larger signals, the output ap-
proaches a square wave for zero input offset and becomes rect-
angular when offset is present. The duty cycle modulation of
this output now produces the nonzero average value. Assume a
maximum required differential output of 100 mV (after averag-
ing in C1 and C2) as shown in Figure 29. R3 through R6 can
now be chosen to provide ±500 µV of correction range, and with
these values the input offset is reduced by a factor of 500. Using
4.7 µF capacitors, the time constant of the network is about
1.2 ms, and its corner frequency is at 13.5 Hz. The closed loop
high-pass corner (for small signals) is, therefore, at 1.35 MHz.
Bandwidth/Dynamic Range Trade-Offs
The first stage noise of the AD640 is 2 nV/√Hz (short circuited
input) and the full bandwidth of the cascaded ten stages is about
150 MHz. Thus, the noise referred to the input is 24.5 µV rms,
or –79 dBm, which would limit the dynamic range to 77 dBs
(–79 dBm to –2 dBm). In practice, the source resistances will
also generate noise, and the full bandwidth dynamic range will
be less than this.
A low-pass filter between U1 and U2 can limit the noise band-
width and extend the dynamic range. The simplest way to do
this is by the addition of a pair of grounded capacitors at the
signal outputs of U1 (shown as C1 and C2 in Figure 32). The
20
1
11
10
U2
U1
A
VE
= –140mV
INPUT
R1
50V
R2
50V
A
VE
= –40mV
R3
4.99kV
R5
4.99kV
–200mV
–700mV
4mA
14mA
20
1
11
10
C1
C2
R4
4.99kV
R6
4.99kV
Figure 29. Feedback Offset Correction Network
–3 dB frequency of the filter must be above the highest fre
quency to be handled by the converter; if not, nonlinearity in
the transfer function will occur. This can be seen intuitively by
noting that the system would then contract to a single AD640 at
very high frequencies (when U2 has very little input). At inter-
mediate frequencies, U2 will contribute less to the output than
would be the case if there were no interstage attenuation, result-
ing in a kink in the transfer function.
More complex filtering may be considered. For example, if the
signal has a fairly narrow bandwidth, the simple chokes shown
in Figure 28 might be replaced by one or more parallel tuned
circuits. Two separate tuned circuits or transformer coupling
should be used to eliminate all undesirable hf common mode
coupling between U1 and U2. The choice of Q for these circuits
requires compromise. Frequency sensitive nonlinearities can
arise at the edges of the band if the Q is set too high; if too low,
the transmission of the signal from U1 to U2 will be affected
even at the center frequency, again resulting in nonlinearity in
the conversion response. In calculating the Q, note that the
resistance from Pins 10 and 11 to ground is 75 Ω. The input
resistance at Pins 1 and 20 is very high, but the capacitances at
these pins must also be factored into the total LCR circuit.
PRACTICAL APPLICATIONS
We show here two applications, using cascaded AD640s to
achieve a wide dynamic range. As already mentioned, the use of
a differential signal path and differential logarithmic outputs
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AD640BPZ

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