AC SPECIFICATIONS
Model AD640J AD640B AD640T
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Units
SIGNAL INPUTS (Pins 1, 20)
Input Capacitance Either Pin to COM 2 2 2 pF
Noise Spectral Density 1 kHz to 10 MHz 2 2 2 nV/√Hz
Tangential Sensitivity BW = 100 MHz –72 –72 –72 dBm
3 dB BANDWIDTH
Each Stage 350 350 350 MHz
All Five Stages Pins 1 & 20 to 10 & 11 145 145 145 MHz
LOGARITHMIC OUTPUTS
5
Slope Current, I
Y
f< = 1 MHz 0.96 1.0 1.04 0.98 1.0 1.02 0.98 1.0 1.02 mA
f = 30 MHz 0.88 0.94 1.00 0.91 0.94 0.97 0.91 0.94 0.97 mA
f = 60 MHz 0.82 0.90 0.98 0.86 0.90 0.94 0.86 0.90 0.94 mA
f = 90 MHz 0.88 0.88 0.88 mA
f = 120 MHz 0.85 0.85 0.85 mA
Intercept, Dual AD640s
10, 11
f< = 1 MHz –90.6 –88.6 –86.6 –90.0 –88.6 –87.6 –90.0 –88.6 –87.6 dBm
f = 30 MHz –87.6 –87.6 –87.6 dBm
f = 60 MHz –86.3 –86.3 –86.3 dBm
f = 90 MHz –83.9 –83.9 –83.9 dBm
f = 120 MHz –80.3 –80.3 –80.3 dBm
AC LINEARITY
–40 dBm to –2 dBm
12
f = 1 MHz 0.5 2.0 0.5 1.0 0.5 1.0 dB
–35 dBm to –10 dBm
12
f = 1 MHz 0.25 1.0 0.25 0.5 0.25 0.5 dB
–75 dBm to 0 dBm
10
f = 1 MHz 0.75 3.0 0.75 1.5 0.75 1.5 dB
–70 dBm to –10 dBm
10
f = 1 MHz 0.5 2.0 0.5 1.0 0.5 1.0 dB
–75 dBm to +15 dBm
13
f = 10 kHz 0.5 3.0 0.5 1.5 0.5 1.5 dB
PACKAGE OPTION
AD640TD
AD640BE AD640TE
AD640]N
20-Lead Ceramic SBDIP Package (D)
20-Terminal Ceramic LCC (E)
20-Lead Plastic DIP Package (N)
20-Lead Plastic Leaded Chip Carrier (P)
AD640JP AD640BP
NUMBER OF TRANSISTORS 155 155 155
NOTES
1
Logarithms to base 10 are used throughout. The response is independent of the sign of V
IN
.
2
Attenuation ratio trimmed to calibrate intercept to 10 mV when in use. It has a temperature coefficient of +0.30%/ °C.
3
Overall gain is trimmed using a ±200 µV square wave at 2 kHz, corrected for the onset of compression.
4
The fully limited signal output will appear to be a square wave; its amplitude is proportional to absolute temperature.
5
Currents defined as flowing into Pin 14. See FUNDAMENTALS OF LOGARITHMIC CONVERSION for full explanation of scaling concepts. Slope is measured
by linear regression over central region of transfer function.
6
The logarithmic intercept in dBV (decibels relative to 1 V) is defined as 20 LOG
10
(V
X
/1 V).
7
The zero-signal current is a function of temperature unless internal temperature compensation (ITC) pin is grounded.
8
Operating in circuit of Figure 24 using ±0.1% accurate values for R
LA
and R
LB.
Includes slope and nonlinearity errors. Input offset errors also included for
V
IN
>3 mV dc, and over the full input range in ac applications.
9
Essentially independent of supply voltages.
10
Using the circuit of Figure 27, using cascaded AD640s and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.
11
For a sinusoidal signal (see EFFECT OF WAVEFORM ON INTERCEPT). Pin 8 on second AD640 must be grounded to ensure temperature stability of intercept
for dual AD640 system.
12
Using the circuit of Figure 24, using single AD640 and offset nulling. Input is sinusoidal, 0 dBm in 50 Ω = 223 mV rms.
13
Using the circuit of Figure 32, using cascaded AD640s and attenuator. Square wave input.
All min and max specifications are guaranteed, but only those in boldface are 100% tested on all production units. Results from those tests are used to calculate
outgoing quality levels.
Specifications subject to change without notice.
THERMAL CHARACTERISTICS
JC
(ⴗC/W)
JA
(ⴗC/W)
25 85
25 85
24 61
20-Lead Ceramic SBDIP Package (D-20)
20-Terminal Ceramic LCC (E-20-1)
20-Lead Plastic DIP Package (N-20)
20-Lead Plastic Leaded Chip Carrier (P-20)
28 75
AD640
REV. D
–3–
(V
S
= ⴞ5 V, T
A
= +25ⴗC, unless otherwise noted)
