AD640
REV. D–6–
INPUT LEVEL – dBm
–2.5
–2.0
0.5
–40
–0.5
0
–1.5
–1.0
OUTPUT CURRENT – mA
–50 –30 –20 –10 0
30MHz
60MHz
90MHz
120MHz
AD640 6V
S
= 5 VOLTS
TEMPERATURE = +258C
Figure 10. AC Response at 30 MHz, 60 MHz, 90 MHz and
120 MHz, vs. dBm Input (Sinusoidal Input)
FREQUENCY – MHz
1.0
DC 30
SLOPE CURRENT – mA
0.95
0.90
0.85
0.80
60 90 120 150
Figure 11. Slope Current, I
Y
, vs. Input Frequency
Figure 12. Baseband Pulse Response of Single AD640,
Inputs of 1 mV, 10 mV and 100 mV
Figure 13. Logarithmic Response and Linearity at 60 MHz,
T
A
for T
A
= –55
C, +25
C, +125
C
INPUT FREQUENCY – MHz
INTERCEPT LEVEL – dBm
90
80
0 12010 20 100 110
89
87
86
85
84
88
30 40 50 60 70 80 90
83
82
81
Figure 14. Intercept Level (dBm) vs. Frequency
(Cascaded AD640s – Sinusoidal Input)
10
0%
5µs
5µs
20mV
20mV
100
90
Figure 15. Baseband Pulse Response of Cascaded
AD640s, Inputs of 0.2 mV, 2 mV, 20 mV and 200 mV
–Typical AC Performance Characteristics
AD640
REV. D –7
CIRCUIT DESCRIPTION
The AD640 uses five cascaded limiting amplifiers to approxi-
mate a logarithmic response to an input signal of wide dynamic
range and wide bandwidth. This type of logarithmic amplifier
has traditionally been assembled from several small scale ICs
and numerous external components. The performance of these
semidiscrete circuits is often unsatisfactory. In particular, the
logarithmic slope and intercept (see FUNDAMENTALS OF
LOGARITHMIC CONVERSION) are usually not very stable
in the presence of supply and temperature variations even after
laborious and expensive individual calibration. The AD640
employs high precision analog circuit techniques to ensure sta-
bility of scaling over wide variations in supply voltage and tem-
perature. Laser trimming, using ac stimuli and operating
conditions similar to those encountered in practice, provides fully
calibrated logarithmic conversion.
Each of the amplifier/limiter stages in the AD640 has a small
signal voltage gain of 10 dB (×3.162) and a –3 dB bandwidth of
350 MHz. Fully differential direct coupling is used throughout.
This eliminates the many interstage coupling capacitors usually
required in ac applications, and simplifies low frequency signal
processing, for example, in audio and sonar systems. The
AD640 is intended for use in demodulating applications. Each
stage incorporates a detector (a full wave transconductance
rectifier) whose output current depends on the absolute value of
its input voltage.
Figure 16 is a simplified schematic of one stage of the AD640.
All transistors in the basic cell operate at near zero collector to
base voltage and low bias currents, resulting in low levels of ther-
mally induced distortion. These arise when power shifts from one
set of transistors to another during large input signals. Rapid
recovery is essential when a small signal immediately follows a
large one. This low power operation also contributes signifi-
cantly to the excellent long-term calibration stability of the AD640.
The complete AD640, shown in Figure 17, includes two bias
regulators. One determines the small signal gain of the amplifier
stages; the other determines the logarithmic slope. These bias
regulators maintain a high degree of stability in the resulting
function by compensating for potentially large uncertainties
in transistor parameters, temperature and supply voltages. A
third biasing block is used to accurately control the logarithmic
intercept.
By summing the signals at the output of the detectors, a good
approximation to a logarithmic transfer function can be achieved.
The lower the stage gain, the more accurate the approximation,
but more stages are then needed to cover a given dynamic
range. The choice of 10 dB results in a theoretical periodic
Q3 Q4 Q5
Q6
Q7
Q8
1.09mA
PTAT
1.09mA
PTAT
R2
85V
565mA
Q2
R1
85V
Q1
Q9
LOG OUT
565mA
Q10
LOG COM
2.18mA
PTAT
R4
75V
R3
75V
SIG OUT
SIG IN
COMMON
–V
S
Figure 16. Simplified Schematic of a Single AD640 Stage
deviation or ripple in the transfer function of ±0.15 dB from the
ideal response when the input is either a dc voltage or a square
wave. The slope of the transfer function is unaffected by the
input waveform; however, the intercept and ripple are waveform
dependent (see EFFECT OF WAVEFORM ON INTERCEPT).
The input will usually be an amplitude modulated sinusoidal
carrier. In these circumstances the output is a fluctuating current at
twice the carrier frequency (because of the full wave detection)
whose average value is extracted by an external low-pass filter,
which recovers a logarithmic measure of the baseband signal.
Circuit Operation
With reference to Figure 16, the transconductance pair Q7, Q8
and load resistors R3 and R4 form a limiting amplifier having a
small signal gain of 10 dB, set by the tail current of nominally
2.18 mA at 27°C. This current is basically proportional to abso-
lute temperature (PTAT) but includes additional current to
compensate for finite beta and junction resistance. The limiting
output voltage is ±180 mV at 27°C and is PTAT. Emitter fol-
lowers Q1 and Q2 raise the input resistance of the stage, provide
level shifting to introduce collector bias for the gain stage and
detectors, reduce offset drift by forming a thermally balanced
quad with Q7 and Q8 and generate the detector biasing across
resistors R1 and R2.
Transistors Q3 through Q6 form the full wave detector, whose
output is buffered by the cascodes Q9 and Q10. For zero input
Q3 and Q5 conduct only a small amount (a total of about
32 µA) of the 565 µA tail currents supplied to pairs Q3–Q4 and
Q5–Q6. This “pedestal” current flows in output cascode Q9 to
the LOG OUT node (Pin 14). When driven to the peak output
of the preceding stage, Q3 or Q5 (depending on signal polarity)
conducts lost of the tail current, and the output rises to 532 µA.
The LOG OUT current has thus changed by 500 µA as the
input has changed from zero to its maximum value. Since the
detectors are spaced at 10 dB intervals, the output increases by
ATN OUT
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
ATN LO
ATN COM
SIG +IN
SIG –IN
ATN COM
COM
27V
30V
270V
ATN IN
1kV
RG1 RG0
RG2
–V
S
BL1
+V
S
LOG OUT
LOG COM
SIG +OUT
SIG –OUT
BL2
ITC
20
1
INTERCEPT POSITIONING BIAS
19
3
2
4
18
5
6
GAIN BIAS REGULATOR
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
10dB 10dB
AMPLIFIER/LIMITER
FULL-WAVE
DETECTOR
17 16 14
13
1kV
7
11
10
9
8
12
SLOPE BIAS REGULATOR
15
10dB10dB
Figure 17. Block Diagram of the Complete AD640
AD640
REV. D–8–
50 µA/dB, or 1 mA per decade. This scaling parameter is
trimmed to absolute accuracy using a 2 kHz square wave. At
frequencies near the system bandwidth, the slope is reduced due
to the reduced output of the limiter stages, but it is still rela-
tively insensitive to temperature variations so that a simple ex-
ternal slope adjustment in restore scaling accuracy.
The intercept position bias generator (Figure 17) removes the
pedestal current from the summed detector outputs. It is ad-
justed during manufacture such that the output (flowing into
Pin 14) is 1 mA when a 2 kHz square-wave input of exactly
±10 mV is applied to the AD640. This places the dc intercept at
precisely 1 mV. The LOG COM output (Pin 13) is the comple-
ment of LOG OUT. It also has a 1 mV intercept, but with an
inverted slope of –1 mA/decade. Because its pedestal is very
large (equivalent to about 100 dB), its intercept voltage is not
guaranteed. The intercept positioning currents include a special
internal temperature compensation (ITC) term which can be
disabled by connecting Pin 8 to ground.
The logarithmic function of the AD640 is absolutely calibrated
to within ±0.3 dB (or ±15 µA) for 2 kHz square-wave inputs of
±1 mV to ±100 mV, and to within ±1 dB between ±750 µV and
±200 mV. Figure 18 is a typical plot of the dc transfer function,
showing the outputs at temperatures of –55°C, +25°C and
+125°C. While the slope and intercept are seen to be little af-
fected by temperature, there is a lateral shift in the endpoints of
the “linear” region of the transfer function, which reduces the
effective dynamic range. The cause of this shift is explained in
Fundamentals of Logarithmic Conversion section.
INPUT VOLTAGE – mV
2.5
0
0.1
OUTPUT CURRENT – mA
1.0 10.0 100.0 1000.0
2
1
0
–1
–2
2.0
1.5
1.0
0.5
–0.5
+1258C
+258C
–558C
+258C
+1258C
–558C
ABSOLUTE ERROR – dB
Figure 18. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at T
A
= –55
°
C, +25
°
C, Input Direct
to Pins 1 and 20
The on chip attenuator can be used to handle input levels 20 dB
higher, that is, from ±7.5 mV to ±2 V for dc or square wave
inputs. It is specially designed to have a positive temperature
coefficient and is trimmed to position the intercept at 10 mV dc
(or –24 dBm for a sinusoidal input) over the full temperature
range. When using the attenuator the internal bias compensa-
tion should be disabled by grounding Pin 8. Figure 19 shows
the output at –55°C, +25°C, +85°C and +125°C for a single
AD640 with the attenuator in use; the curves overlap almost
perfectly, and the lateral shift in the transfer function does not
occur. Therefore, the full dynamic range is available at all
temperatures.
The output of the final limiter is available in differential form at
Pins 10 and 11. The output impedance is 75 to ground from
either pin. For most input levels, this output will appear to have
INPUT VOLTAGE – mV
2.5
0
1
OUTPUT CURRENT – mA
10 100 1000 10000
1
0
–1
–2
2.0
1.5
1.0
0.5
–0.5
+258C
+858C
+1258C
–558C
ABSOLUTE ERROR – dB
Figure 19. Logarithmic Output and Absolute Error vs. DC
or Square Wave Input at T
A
= –55
°
C, +25
°
C, +85
°
C and
+125
°
C, Input via On-Chip Attenuator
roughly a square waveform. The signal path may be extended
using these outputs (see OPERATION OF CASCADED
AD640s). The logarithmic outputs from two or more AD640s
can be directly summed with full accuracy.
A pair of 1 k applications resistors, RG1 and RG2 (Figure 17)
are accessed via Pins 15, 16 and 17. These can be used to con-
vert an output current to a voltage, with a slope of 1 V/decade
(using one resistor), 2 V/decade (both resistors in series) or
0.5 V/decade (both in parallel). Using all the resistors from two
AD640s (for example, in a cascaded configuration) ten slope
options from 0.25 V to 4 V/decade are available.
FUNDAMENTALS OF LOGARITHMIC CONVERSION
The conversion of a signal to its equivalent logarithmic value
involves a nonlinear operation, the consequences of which can be
very confusing if not fully understood. It is important to realize
from the outset that many of the familiar concepts of linear
circuits are of little relevance in this context. For example, the
incremental gain of an ideal logarithmic converter approaches
infinity as the input approaches zero. Further, an offset at the
output of a linear amplifier is simply equivalent to an offset at
the input, while in a logarithmic converter it is equivalent to a
change of amplitude at the input—a very different relationship.
We assume a dc signal in the following discussion to simplify the
concepts; ac behavior and the effect of input waveform on cali-
bration are discussed later. A logarithmic converter having a
voltage input V
IN
and output V
OUT
must satisfy a transfer func-
tion of the form
V
OUT
= V
Y
LOG (V
IN
/V
X
) Equation (1)
where Vy and Vx are fixed voltages which determine the scaling
of the converter. The input is divided by a voltage because the
argument of a logarithm has to be a simple ratio. The logarithm
must be multiplied by a voltage to develop a voltage output.
These operations are not, of course, carried out by explicit com-
putational elements, but are inherent in the behavior of the
converter. For stable operation, V
X
and V
Y
must be based on
sound design criteria and rendered stable over wide temperature
and supply voltage extremes. This aspect of RF logarithmic
amplifier design has traditionally received little attention.
When V
IN
= V
X
, the logarithm is zero. V
X
is, therefore, called
the Intercept Voltage, because a graph of V
OUT
versus LOG (V
IN
)
—ideally a straight line—crosses the horizontal axis at this point

AD640BPZ

Mfr. #:
Manufacturer:
Description:
Logarithmic Amplifiers LOGARITHMIC AMP IC 120MHz 50dB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union