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74HC7046AD,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
December 1990 13
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
OTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
R
S
resistor range 50
50
50
300
300
300
kΩ 3.0
4.5
6.0
at R
S
> 300 kΩ
the leakage
current can
influence
V
DEMOUT
V
OFF
offset voltage
VCO
IN
to V
DEMOUT
±30
±20
±10
mV 3.0
4.5
6.0
V
I
=V
VCOIN
=
1/2 V
CC
;
values taken
over R
S
range;
see Fig.13
R
D
dynamic output
resistance at DEM
OUT
25
25
25
Ω 3.0
4.5
6.0
V
DEMOUT
=
1/2 V
CC
December 1990 14
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
AC CHARACTERISTICS FOR 74HC
Phase comparator section
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF
VCO section
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
OTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
SIG
IN
, COMP
IN
to PC1
OUT
58
21
17
200
40
34
250
50
43
300
60
51
ns 2.0
4.5
6.0
Fig.14
t
PZH
/ t
PZL
3-state output enable
time SIG
IN
, COMP
IN
to PC2
OUT
74
27
22
280
56
48
350
70
60
420
84
71
ns 2.0
4.5
6.0
Fig.15
t
PHZ
/ t
PLZ
3-state output disable
time SIG
IN
, COMP
IN
to PC2
OUT
96
35
28
325
65
55
405
81
69
490
98
83
ns 2.0
4.5
6.0
Fig.15
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.14
V
I(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIG
IN
or COMP
IN
9
11
15
33
mV 2.0
3.0
4.5
6.0
f
i
= 1 MHz
SYM-
BOL
PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
OTHER
+25 −40 to +85 −40
to +125
min. typ. max. typ. max. min. max.
∆f/T frequency stability
with temperature
change
0.20
0.15
0.14
%/K 3.0
4.5
6.0
V
I
=V
VCOIN
=1/2 V
CC
;
R1 = 100 kΩ; R2 = ∞;
C1 = 100 pF; see Fig.16
f
o
VCO centre
frequency
(duty factor = 50%)
7.0
11.0
13.0
10.0
17.0
21.0
MHz 3.0
4.5
6.0
V
VCOIN
= 1/2 V
CC
;
R1 = 3 kΩ; R2 = ∞;
C1 = 40 pF; see Fig.17
∆f
VCO
VCO frequency
linearity
1.0
0.4
0.3
% 3.0
4.5
6.0
R1 = 100 kΩ; R2 = ∞;
C1 = 100 pF; see Figs 18
and 19
δ
VCO
duty factor at
VCO
OUT
50
50
50
% 3.0
4.5
6.0
December 1990 15
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
DC CHARACTERISTICS FOR 74HCT
Quiescent supply current
Voltages are referenced to GND (ground = 0 V)
Note
1. The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given above.
To determine ∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
OTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
I
CC
quiescent supply current
(VCO disabled)
8.0 80.0 160.0 µA 6.0 pins 3, 5 and 14
at V
CC
; pin 9 at
GND; I
I
at pins 3
and 14 to be
excluded
∆I
CC
additional quiescent
supply current per input
pin for unit load coefficient
is 1 (note 1)
V
I
=V
CC
− 2.1 V
100 360 450 490 µA 4.5
to
5.5
pins 3 and 14 at
V
CC
; pin 9 at
GND; I
I
at pins 3
and 14 to be
excluded
INPUT UNIT LOAD COEFFICIENT
INH 1.00
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

74HC7046AD,118

Mfr. #:
Buy 74HC7046AD,118
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL PHASE LOCKED LOOP
Lifecycle:
New from this manufacturer.
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