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74HC7046AD,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
December 1990 16
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
Phase comparator section
Voltages are referenced to GND (ground = 0 V)
SYM
BOL
PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
V
I
OTHER+25 −40 to +85 −40 to +125
min. typ. max min. max. min. max.
V
IH
DC coupled
HIGH level input voltage
SIG
IN
, COMP
IN
3.15 2.4 V 4.5
V
IL
DC coupled
LOW level input voltage
SIG
IN
, COMP
IN
2.1 1.35 V 4.5
V
OH
HIGH level output voltage
LD, PC
nOUT
4.4 4.5 4.4 4.4 V 4.5
V
IH
or
V
IL
−I
O
=20µA
V
OH
HIGH level output voltage
LD, PC
nOUT
3.98 4.32 3.84 3.7 V 4.5
V
IH
or
V
IL
−I
O
= 4.0 mA
V
OL
LOW level output voltage
LD, PC
nOUT
0 0.1 0.1 0.1 V 4.5
V
IH
or
V
IL
I
O
=20µA
V
OL
LOW level output voltage
LD, PC
nOUT
0.15 0.26 0.33 0.4 V 4.5
V
IH
or
V
IL
I
O
= 4.0 mA
±I
I
input leakage current
SIG
IN
, COMP
IN
30 38 45 µA 5.5
V
CC
or
GND
±I
OZ
3-state
OFF-state current
PC2
OUT
0.5 5.0 10.0 µA 5.5
V
IH
or
V
IL
V
O
=V
CC
or GND
R
I
input resistance
SIG
IN
, COMP
IN
250 kΩ 4.5
V
I
at self-bias
operating point;
∆V
I
= 0.5 V; see Figs
10, 11 and 12
December 1990 17
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
DC CHARACTERISTICS FOR 74HCT
VCO section
Voltages are referenced to GND (ground = 0 V)
Note
1. The parallel value of R1 and R2 should be more than 2.7 kΩ. Optimum performance is achieved when R1 and/or R2
are/is > 10 kΩ.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
V
I
OTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
V
IH
HIGH level input
voltage
INH
2.0 1.6 2.0 2.0 V 4.5
to
5.5
V
IL
LOW level input
voltage
INH
1.2 0.8 0.8 0.8 V 4.5
to
5.5
V
OH
HIGH level output
voltage
VCO
OUT
4.4 4.5 4.4 4.4 V 4.5 V
IH
or
V
IL
−I
O
=20µA
V
OH
HIGH level output
voltage
VCO
OUT
3.98 4.32 3.84 3.7 V 4.5 V
IH
or
V
IL
−I
O
= 4.0 mA
V
OL
LOW level output
voltage
VCO
OUT
0 0.1 0.1 0.1 V 4.5 V
IH
or
V
IL
I
O
=20µA
V
OL
LOW level output
voltage
VCO
OUT
0.15 0.26 0.33 0.4 V 4.5 V
IH
or
V
IL
I
O
= 4.0 mA
V
OL
LOW level output
voltage C1
A
, C1
B
(test purposes only)
0.40 0.47 0.54 V 4.5 V
IH
or
V
IL
I
O
= 4.0 mA
±I
I
input leakage
current
INH, VCO
IN
0.1 1.0 1.0 µA 5.5 V
CC
or
GND
R1 resistor range 3.0 300 kΩ 4.5 note 1
R2 resistor range 3.0 300 kΩ 4.5 note 1
C1 capacitor range 40 no
limit
pF 4.5
V
VCOIN
operating voltage
range at VCO
IN
1.1 3.4 V 4.5 over the range
specified for
R1;
for linearity see
Figs 18 and 19.
December 1990 18
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
AC CHARACTERISTICS FOR 74HCT
Phase comparator section
GND = 0 V; t
r
=t
f
= 6 ns; C
L
= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
OTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
R
S
resistor range 50 300 kΩ 4.5 at R
S
> 300 kΩ the
leakage current can
influence V
DEMOUT
V
OFF
offset voltage
VCO
IN
to V
DEMOUT
±20 mV 4.5 V
I
=V
VCOIN
= 1/2
V
CC
; values taken
over R
S
range;
see Fig.13
R
D
dynamic output
resistance at DEM
OUT
25 Ω 4.5 V
DEMOUT
= 1/2 V
CC
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST
CONDITIONS
74HCT
V
CC
(V)
OTHER+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
SIG
IN
, COMP
IN
to PC1
OUT
21 40 50 60 ns 4.5 Fig.14
t
PZH
/ t
PZL
3-state output enable
time SIG
IN
, COMP
IN
to PC2
OUT
27 56 70 84 ns 4.5 Fig.15
t
PHZ
/ t
PLZ
3-state output disable
time SIG
IN
, COMP
IN
to PC2
OUT
35 65 81 98 ns 4.5 Fig.15
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.14
V
I(p-p)
AC coupled input sensitivity
(peak-to-peak value) at
SIG
IN
or COMP
IN
15 mV 4.5 f
i
=
1 MHz
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

74HC7046AD,118

Mfr. #:
Buy 74HC7046AD,118
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL PHASE LOCKED LOOP
Lifecycle:
New from this manufacturer.
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