December 1990 34
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
Fig.32 C
LD
capacitor value versus typical t
LD
.
C
LD
= capacitor connected to pin 15
(includes the parasitic input capacitance of the IC, approximately 3.5 pF).
t
LD
= phase difference between SIG
IN
and COMP
IN
(positive-going edges).
December 1990 35
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
The maximum permitted phase error
must be defined, before t
LD
can be
defined using the following formula:
Using this calculated value in Fig.32,
it is possible to define the value of
C
LD
, e.g. assuming the phase error is
36° and f
IN
= 2 MHz:
and using Fig.32, it can be seen that
C
LD
is 26 pF.
With the addition of one retriggerable
monostable (e.g. “123”, “423” or
“4538”) a steady state LOW and
HIGH indication can be obtained, as
shown in Fig.33.
t
LD
φ
max
360
------------
1
f
IN
------
× .=
t
LD
36°
360
----------
1
2MHz
-----------------
× 50 ns,==
Fig.33 Steady state signal for lock indication.
December 1990 36
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
PLL design example
The frequency synthesizer, used in the design example
shown in Fig.34, has the following parameters:
Output frequency: 2 MHz to 3 MHz
frequency steps : 100 kHz
settling time : 1 ms
overshoot : < 20%
The open-loop gain is H (s) x G (s) = K
p
× K
f
× K
o
× K
n
.
Where:
The programmable counter ratio K
n
can be found as
follows:
The VCO is set by the values of R1, R2 and C1,
R2 = 10 k (adjustable). The values can be determined
using the information in the section “DESIGN
CONSIDERATIONS”.
With f
o
= 2.5 MHz and f
L
= 500 kHz this gives the following
values (V
CC
= 5.0 V):
R1 = 10 k
R2 = 10 k
C1 = 500 pF
The VCO gain is:
The gain of the phase comparator is:
The transfer gain of the filter is given by:
Where:
K
p
= phase comparator gain
K
f
= low-pass filter transfer gain
K
o
=K
v
/s VCO gain
K
n
= 1/n divider ratio
N
min.
f
out
f
step
-----------
2 MHz
100 kHz
----------------------
20== =
N
max.
f
out
f
step
-----------
3MHz
100 kHz
----------------------
30== =
K
V
2f
L
2 π××
0.9 V
CC
0.9()
----------------------------------------------
1MHz
3.2
-----------------
2 π× 210
6
× r/s/v===
K
p
V
CC
4 π×
------------
0.4 V/r.==
K
f
1τ
2
s+
1τ
1
τ
2
+()s+
-------------------------------------
=
τ
1
R3C2 and τ
2
R4C2.==
The characteristics equation is:
1 + H (s) × G (s) = 0.
This results in:
The natural frequency ω
n
is defined as follows:
and the damping value ζ is defined as follows:
The overshoot and settling time percentages are now used
to determine ω
n
. From Fig.35 it can be seen that the
damping ratio ζ = 0.8 will produce an overshoot of less
than 20% and settle to within 5% at ω
n
t = 4.5. The required
settling time is 1 ms. This results in:
Rewriting the equation for natural frequency results in:
The maximum overshoot occurs at N
max
.:
When C2 = 470 nF, then
R3 is calculated using the damping ratio equation:
s
2
1K
p
K
v
K
n
×τ
2
××+
τ
1
τ
2
+()
-----------------------------------------------------
s
K
p
K
v
× K
n
×
τ
1
τ
2
+()
--------------------------------
0.=++
ω
n
K
p
K
v
×K
n
×
τ
1
τ
2
+()
--------------------------------
˙
.=
ζ
1
2 ω
n
----------
1K
p
K
v
× K
n
×τ
2
×+
τ
1
τ
2
+
-----------------------------------------------------
× .=
ω
n
5
t
---
5
0.001
---------------
510
3
× r/s.== =
τ
1
τ
2
+()
K
p
K
v
×K
n
×
ω
n
2
--------------------------------
.=
τ
1
τ
2
+()
0.4 2× 10
6
×
5000
2
30×
---------------------------------
0.0011 s.==
R4
τ
1
τ
2
+()2ω
n
×ζ1××
K
p
K
v
×K
n
×
-----------------------------------------------------------------
790 .==
R3
τ
1
C2
--------
R4 2 k.==

74HC7046AD,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL PHASE LOCKED LOOP
Lifecycle:
New from this manufacturer.
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