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74HC7046AD,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
December 1990 28
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
VCO frequency characteristic
VCO frequency
with extra
offset
PC1, PC2 With R1 and R2 within the ranges 3 kΩ< R1 < 300 kΩ, 3 kΩ<R2 < 300 kΩ,
the characteristics of the VCO operation will be as shown in Fig. 24.
Fig. 24 Frequency characteristic of VCO operating with offset:
f
o
= centre frequency; 2f
L
= frequency lock range.
Selection of R1, R2 and C1
PC1, PC2 Given f
0
and f
L
, determine the value of product R1C1 by using Fig.29.
Calculate f
off
from the equation f
off
=f
o
−1.6f
L
.
Obtain the values of C1 and R2 by using Fig.28.
Calculate the value of R1 from the value of C1 and the product R1C1.
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
December 1990 29
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
PLL conditions
with no signal at
the SIG
IN
input
PC1 VCO adjusts to f
o
with φ
DEMOUT
=90° and V
VCOIN
= 1/2 V
CC
(see Fig.6).
PC2 VCO adjusts to f
o
with φ
DEMOUT
= −360° and V
VCOIN
= min. (see Fig.8).
PLL frequency
capture range
PC1, PC2
Loop filter component selection
(a) τ = R3 x C2 (b) amplitude characteristic (c) pole-zero diagram
Fig. 25 Simple loop filter for PLL without offset; R3 ≥ 500 Ω.
(a) τ1 = R3 x C2; (b) amplitude characteristic (c) pole-zero diagram
τ2 = R4 x C2;
τ3 = (R3 + R4) x C2
Fig. 26 Simple loop filter for PLL with offset; R3 + R4 ≥ 500 Ω.
PLL locks on
harmonics at
centre frequency
PC1 yes
PC2 no
noise rejection at
signal input
PC1 high
PC2 low
AC ripple content
when PLL is
locked
PC1 f
r
=2f
i
, large ripple content at φ
DEMOUT
=90°
PC2 f
r
=f
i
, small ripple content at φ
DEMOUT
=0°
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
December 1990 30
Philips Semiconductors Product specification
Phase-locked-loop with lock detector 74HC/HCT7046A
Fig.27 Typical value of VCO centre frequency (f
o
) as a function of C1: R2 = ∞; V
VCOIN
= 1/2 V
CC
; INH = GND;
T
amb
=25°C.
(1) To obtain optimum VCO performance, C1 must be as small as possible but larger than 100 pF.
(2) Interpolation for various values of R1 can be easily calculated because a constant R1C1 product will produce
almost the same VCO output frequency.
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74HC7046AD,118

Mfr. #:
Buy 74HC7046AD,118
Manufacturer:
NXP Semiconductors
Description:
Phase Locked Loops - PLL PHASE LOCKED LOOP
Lifecycle:
New from this manufacturer.
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