KAI−0330
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3
DEVICE DESCRIPTION
Architecture
Figure 2. Functional Block Diagram
fV1
fV2
fV2
fV1
fR
Horizontal Register A
10 dummies 4 dummies
Horizontal Register B
H1A
H2
H1B
WELL
G
G
R
B
Color Filter Pattern
8 Dark Lines at Top of Image
4 Dark Lines at Bottom of Image
8 Dark Columns
24 Dark Columns
KAI−0330
Active Image Area
648 (H) × 484 (V)
9.0 × 9.0 mm Pixels
V
RD
V
DD
V
OUTA
V
SS
/OG
V
DD
V
OUTB
V
SS
/OG
V
SUB
The KAI−0330 consists of 648 × 484 photodiodes, 680
vertical (parallel) CCD shift registers (VCCDs), and dual
496 pixel horizontal (serial) CCD shift registers (HCCDs)
with independent output structures. The device can be
operated in either single or dual line mode. The advanced,
progressive-scan architecture of the device allows the entire
image area to be read out in a single scan. The active pixels
are surrounded by an additional 32 columns and 12 rows of
light-shielded dark reference pixels.
Image Acquisition
An electronic representation of an image is formed when
incident photons falling on the sensor plane create
electron-hole pairs within the individual silicon
photodiodes. These photoelectrons are collected locally by
the formation of potential wells at each photosite. Below
photodiode saturation, the number of photoelectrons
collected at each pixel is linearly dependent on light level
and exposure time and non-linearly dependent on
wavelength. When the photodiode’s charge capacity is
reached, excess electrons are discharged into the substrate to
prevent blooming.
Charge Transport
The accumulated or integrated charge from each
photodiode is transported to the output by a three-step
process. The charge is first transported from the photodiodes
to the VCCDs by applying a large positive voltage to the
phase-one vertical clock (fV1). This reads out every row, or
line, of photodiodes into the VCCDs.
The charge is then transported from the VCCDs to the
HCCDs line by line. Finally, the HCCDs transport these
rows of charge packets to the output structures pixel by
pixel. On each falling edge of the horizontal clock, fH2,
these charge packets are dumped over the output gate (OG,
Figure 3) onto the floating diffusion (FDA and FDB,
Figure 3).
Both the horizontal and vertical shift registers use
traditional two-phase complementary clocking for charge
transport. Transfer to the HCCDs begins when fV2 is
clocked high and then low (while holding fH1A high)
causing charge to be transferred from fV1 to fV2 and
subsequently into the A HCCD. The A register can now be
read out in single line mode. If it is desired to operate the
device in a dual line readout mode for higher frame rates, this
line is transferred into the B HCCD by clocking fH1A to
a low state, and fH1B to a high state while holding fH2 low.
After fH1A is returned to a high state, the next line can be
transferred into the A HCCD. After this clocking sequence,
both HCCDs are read out in parallel.
The charge capacity of the horizontal CCDs is slightly
more than twice that of the vertical CCDs. This feature
allows the user to perform two-to-one line aggregation in the
charge domain during V-to-H transfer. This device is also
equipped with a fast dump feature that allows the user to
selectively dump complete lines (or rows) of pixels at a time.
This dump, or line clear, is also accomplished during the
V-to-H transfer time by clocking the fast dump gate.
