KAI−0330
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4
Output Structure
Charge packets contained in the horizontal register are
dumped pixel by pixel, onto the floating diffusion output
node whose potential varies linearly with the quantity of
charge in each packet. The amount of potential change is
determined by the expression DV
FD
= DQ/C
FD
.
A three-stage source-follower amplifier is used to buffer
this signal voltage off chip with slightly less than unity gain.
The translation from the charge domain to the voltage
domain is quantified by the output sensitivity or charge to
voltage conversion in terms of mV/e
. After the signal has
been sampled off-chip, the reset clock (fR) removes the
charge from the floating diffusion and resets its potential to
the reset-drain voltage (V
RD
).
Figure 3. Output Structure
f
R
HCCDA
HCCDB
RD
FDB (n/c)
FDA (n/c)
NOTE: For the single output version, V
OUTB
is not active.
V
WELL
V
SUB
V
OUTB
V
OUTA
V
DD
V
SS
& OG
Electronic Shutter
The KAI−0330 provides a structure for the prevention of
blooming which may be used to realize a variable exposure
time as well as performing the anti-blooming function. The
anti-blooming function limits the charge capacity of the
photodiode by draining excess electrons vertically into the
substrate (hence the name Vertical Overflow Drain or
VOD). This function is controlled by applying a large
potential to the device substrate (device terminal SUB). If a
sufficiently large voltage pulse (VES 40 V) is applied to
the substrate, all photodiodes will be emptied of charge
through the substrate, beginning the integration period.
After returning the substrate voltage to the nominal value,
charge can accumulate in the diodes and the charge packet
is subsequently readout onto the VCCD at the next
occurrence of the high level on fV1. The integration time is
then the time between the falling edges of the substrate
shutter pulse and fV1. This scheme allows electronic
variation of the exposure time by a variation in the clock
timing while maintaining a standard video frame rate.
Application of the large shutter pulse must be avoided
during the horizontal register readout or an image artifact
will appear due to feed-through. The shutter pulse VES must
be “hidden” in the horizontal retrace interval. The
integration time is changed by skipping the shutter pulse
from one horizontal retrace interval to another.
The smear specification is not met under electronic shutter
operation. Under constant light intensity and spot size, if the
electronic exposure time is decreased, the smear signal will
remain the same while the image signal will decrease
linearly with exposure. Smear is quoted as a percentage of
the image signal and so the percent smear will increase by
the same factor that the integration time has decreased. This
effect is basic to interline devices.
Extremely bright light can potentially harm solid state
imagers such as Charge-Coupled Devices (CCDs). Refer to
Application Note Using Interline CCD Image Sensors in
High Intensity Visible Lighting Conditions.
KAI−0330
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5
Physical Description
Pin Description and Device Orientation
Figure 4. Pinout Diagram (Top View)
V
OUTA
1
V
SS
/OG 2
fR3
V
RD
4
V
OUTB
5
V
WELL
6
fH2 7
V
WELL
8
fH1B 9
20 V
DD
19 FDG
18 fV2O
17 fV2E
16 V
WELL
15 fV1E
14 fV1O
13 V
WELL
12 fH1A
Pixel 1, 1
V
SUB
10
11 V
SUB
Table 4. PIN DESCRIPTION
Pin No.
Symbol Description
1 V
OUTA
Video Output Channel A
2 V
SS
/OG Output Amplifier Return and OG
3
fR
Reset Clock
4 V
RD
Reset Drain
5 V
OUTB
Video Output Channel B (Note 1)
6, 8, 13, 16 V
WELL
P-Well (Ground)
7
fH2
A & B Horizontal CCD Clock − Phase 2
9
fH1B
B Horizontal CCD Clock − Phase 1
10, 11 V
SUB
Substrate
12
fH1A
A Horizontal CCD Clock − Phase 1
14
fV1O
Vertical CCD Clock − Phase 1, Odd Field (Note 2)
15
fV1E
Vertical CCD Clock − Phase 1, Even Field (Note 2)
17
fV2E
Vertical CCD Clock − Phase 2, Even Field (Note 3)
18
fV2O
Vertical CCD Clock − Phase 2, Odd Field (Note 3)
19 FDG Fast Dump Gate
20 V
DD
Output Amplifier Supply
1. For the single output version, V
OUTB
is not active.
2. Pins 14 and 15 must be connected together − only 1 Phase 1 clock driver is required.
3. Pins 17 and 18 must be connected together − only 1 Phase 2 clock driver is required.
KAI−0330
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6
IMAGING PERFORMANCE
All the following values were derived using nominal
operating conditions using the recommended timing. Unless
otherwise stated, readout time = 40 ms, integration time =
40 ms and sensor temperature = 40°C. Correlated double
sampling of the output is assumed and recommended. Many
units are expressed in electrons, to convert to voltage,
multiply by the amplifier sensitivity.
Defects are excluded from the following tests and the
signal output is referenced to the dark pixels at the end of
each line unless otherwise specified.
Table 5. ELECTRO-OPTICAL FOR KAI−0330−CBA
Parameter
Symbol Min. Nom. Max. Unit
Optical Fill Factor F 55.0 %
Saturation Exposure (Note 1) E
SAT
0.046
mJ/cm
2
Red Peak Quantum Efficiency l = 620 nm (Note 2)
QE
R
25 %
Green Peak Quantum Efficiency l = 530 nm (Note 2)
QE
G
26 %
Blue Peak Quantum Efficiency l = 460 nm (Note 2)
QE
B
32 %
Green Photoresponse Shading (Note 4) R
GS
6 %
Photoresponse Non-Uniformity (Note 3) PRNU 5.0 p-p %
Photoresponse Non-Linearity PRNL 5.0 %
Amplifier Sensitivity
DV/DN
11.5
mV/e
1. For l = 530 nm wavelength, and V
SAT
= 350 mV.
2. Refer to typical values from Figure 5.
3. Under uniform illumination with output signal equal to 280 mV.
4. This is the global variation in chip output for green pixels across the entire chip.
5. It is recommended to use low-pass filter with l
CUT-OFF
at ~ 680 nm for high performance.
Table 6. ELECTRO-OPTICAL FOR KAI−0330−ABA
Parameter Symbol Min. Nom. Max. Unit
Optical Fill Factor F 55.0 %
Saturation Exposure (Note 1) E
SAT
0.037
mJ/cm
2
Peak Quantum Efficiency (Note 2) QE 36 %
Photoresponse Non-Uniformity (Note 3) PRNU 5.0 p-p %
Photoresponse Non-Linearity PRNL 5.0 %
1. For l = 550 nm wavelength, and V
SAT
= 350 mV.
2. Refer to typical values from Figure 6.
3. Under uniform illumination with output signal equal to 280 mV.
Table 7. CCD IMAGE SPECIFICATIONS
Parameter
Symbol Min. Nom. Max. Unit
Output Saturation Voltage (Notes 1, 2, 8) V
SAT
350 mV
Dark Current I
D
0.5 nA
Dark Current Doubling Temperature DCDT 7 8 10 °C
Charge Transfer Efficiency (Notes 2, 3) CTE 0.99999
Horizontal CCD Frequency (Note 4) f
H
30 MHz
Image Lag (Note 5) IL 100 e
Blooming Margin (Notes 6, 8) X
AB
100
Vertical Smear (Note 7) Smr 0.01 %
1. V
SAT
is the green pixel mean value at saturation as measured at the output of the device with X
AB
= 1. V
SAT
can be varied by adjusting V
SUB
.
2. Measured at sensor output.
3. With stray output load capacitance of C
L
= 10 pF between the output and AC ground.
4. Using maximum CCD frequency and/or minimum CCD transfer times may compromise performance.
5. This is the first field decay lag measured by strobe illuminating the device at (H
SAT
,V
SAT
), and by then measuring the subsequent frame’s
average pixel output in the dark.
6. X
AB
represents the increase above the saturation-irradiance level (H
SAT
) that the device can be exposed to before blooming of the vertical
shift register will occur. It should also be noted that V
OUT
rises above V
SAT
for irradiance levels above H
SAT
, as shown in Figure 8.
7. Measured under 10% (~100 lines) image height illumination with white light source and without electronic shutter operation and below V
SAT
.
8. It should be noted that there is tradeoff between X
AB
and V
SAT
.

KAI-0330-ABA-CB-AA-SINGLE

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Image Sensor Monochrome CCD 648x484Pixels 20-Pin CDIP UNTBX
Lifecycle:
New from this manufacturer.
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