KAI−0330
www.onsemi.com
13
Figure 11. Recommended Output Structure Load Diagram
0.1 mF
5 mA
140 W
1 kW
V
OUT
2N3904 or
Equivalent
Buffered
Output
AC Clock Level Conditions
Table 15. CLOCK LEVELS
Description Symbol Level Min. Nom. Max. Unit Pin Impedance
Vertical CCD Clock
fV1 Low −10.0 −9.5 −9.0 V 25 nF, > 1.2 MW
Mid 0.0 0.2 0.4 V
High 8.5 9.0 9.5 V
Vertical CCD Clock
fV2 Low −10.0 −9.5 −9.0 V 25 nF, > 1.2 MW
High 0.0 0.2 0.4 V
f1 Horizontal CCD A Clock fH1A Low −7.5 −7.0 −6.5 V 100 pF, > 1.2 MW
High 2.5 3.0 3.5 V
f1 Horizontal CCD B Clock
(Single Register Mode)
(Note 4)
fH1B
Low −7.5 −7.0 −6.5 V
100 pF, > 1.2 MW
f1 Horizontal CCD B Clock
(Dual Register Mode)
(Note 4)
fH1B Low −7.5 −7.0 −6.5 V 100 pF, > 1.2 MW
High 2.5 3.0 3.5 V
f2 Horizontal CCD Clock fH2 Low −7.5 −7.0 −6.5 V 125 pF, > 1.2 MW
High 2.5 3.0 3.5 V
Reset Clock
fR Low −6.5 −6.0 −5.5 V 5 pF, > 1.2 MW
High −0.5 0.0 0.5 V
Fast Dump Gate Clock
(Note 3)
fFDG Low −5.5 −5.0 −4.5 V 20 pF, > 1.2 MW
High 4.5 5.0 5.5 V
1. The AC and DC operating levels are for room temperature operation. Operation at other temperatures may or may not require adjustments
of these voltages.
2. Pins shown with impedance greater than 1.2 MW are expected resistances. These pins are only verified to 1.2 MW.
3. When not used, refer to DC operating condition.
4. For single register mode, set fH1B to −7.0 V at all times rather than clocking it.
This device is suitable for a wide range of applications
requiring a variety of different operating conditions. Consult
ON Semiconductor in those situations in which operating
conditions meet or exceed minimum or maximum levels.
