MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-of-
Load, Tracking, and DDR Memory Power Supplies
______________________________________________________________________________________ 19
GAIN
(dB)
0
f
Z1
f
Z2
f
C
f
P2
f
P3
FREQUENCY
EA GAIN
CLOSED-LOOP GAIN
Figure 7. Closed-Loop and Error-Amplifier Gain Plot for Case 2
C1
R3
R1
R2
V
OUT FB
REF
EA
COMP
C2
C3
R4
GAIN
(dB)
0
f
z1
f
Z2
f
C
f
P2
f
P3
FREQUENCY
EA GAIN
CLOSED-LOOP GAIN
Figure 6. Error-Amplifier Compensation Circuit; Closed-Loop and Error-Amplifier Gain Plot for Case 1
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-of-
Load, Tracking, and DDR Memory Power Supplies
20 ______________________________________________________________________________________
FREQ
OSC
EN1
EN2
COMP1
AVL
REFIN
SS2
GND
COMP2
ILIM1
BST1
DH1
LX1
DL1
PGND
V+
VL
SS1
FB1
POK1
VTTR
ILIM2
BST2
DH2
LX2
VL
DL2
PGND
POK2
FB2
OVP2
UVP2
200µA
UVP1
OVP1
IMAX
SENSE
PWM
EAMP
SOFT-START
SOFT-START
EAMP
IMAX
SENSE
PWM
EAMP
CONTROL
LOGIC
0.936V
0.80V
0.560V
0.896V
1V
0.704V
CONTROL
LOGIC
BIAS
REF
0.7REFIN 1.17REFIN
1.12REFIN
0.88REFIN
REFIN
REFIN
VL
VL
200µA
MAX8537/MAX8539 Functional Diagram
MAX8537/MAX8538/MAX8539
Dual-Synchronous Buck Controllers for Point-of-
Load, Tracking, and DDR Memory Power Supplies
______________________________________________________________________________________ 21
Case 2: Crossover frequency is greater than the
output-capacitor ESR zero (f
C
> f
Z_ESR
).
The modulator gain at f
C
is:
G
MOD(FC)
= G
MOD(DC)
x (f
P_LC
)
2
/ (f
Z_ESR
x f
C
)
Since the output-capacitor ESR-zero frequency is high-
er than the LC double-pole frequency but lower than
the closed-loop crossover frequency, where the modu-
lator already has -1 slope, the error-amplifier gain must
have zero slope at f
C
so the loop crosses over at the
desired -1 slope.
The error-amplifier circuit configuration is the same as
case 1 above; however, the closed-loop crossover fre-
quency is now between f
P2
and f
P3
as illustrated in
Figure 7.
The equations that define the error amplifier’s zeros
(f
Z1_EA
, f
Z2_EA
) and poles (f
P2_EA
, f
P3_EA
) are the same
as case 1; however, f
P2_EA
is now lower than the
closed-loop crossover frequency. Therefore, the error-
amplifier gain between f
Z1_EA
and f
Z2_EA
is now calcu-
lated as:
G
EA
(f
Z1_EA
- f
Z2_EA
) = G
EA(FC)
x f
Z2_EA
/ f
P2_EA
=
f
Z2_EA
/ (f
P2_EA
x G
MOD(FC)
)
This gain is set by the ratio of R4/R1, where R1 is calcu-
lated in the Output Voltage Setting section. Thus:
R4 = R1 x f
Z2_EA
/ (f
P2_EA
x G
MOD(FC)
)
where f
Z2_EA
= f
P_LC
and f
P2_EA
= f
Z_ESR
.
Similar to case 1, C2 can be calculated as:
C2 = 2 / (π x R4 x f
P_LC
)
Set the error-amplifier third pole, f
P3_EA
, at half the
switching frequency, and let R
I
= (R1 x R3) / (R1 + R3).
The gain of the error amplifier between f
P2_EA
and
f
P3_EA
is set by the ratio of R4/R
I
and is equal to
G
EA(FC)
= 1 / G
MOD(FC)
. Then:
R
I
= R4 x G
MOD(FC)
Similar to case 1, R3, C1, and C3 can be calculated as:
R3 = R1 x Ri / (R1 - R
I
)
C1 = 1 / (2π x R3 x f
Z_ESR
)
C3 = C2 / ((2π x C2 x R4 x f
P3_EA
) - 1)
Applications Information
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. The
switching-power stage requires particular attention.
Follow these guidelines for good PC board layout:
1) Place the decoupling capacitors as close to the IC
pins as possible.
REFIN
SS2
FB2
COMP2
FREQ
EN1
EN2
POK2
DL2
POK1
ILIM2
LX2
DH2
BST2
TOP VIEW
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BST1
DH1
LX1
ILIM1
PGND
DL1
GND
VL
V+
AVL
VTTR
COMP1
FB1
SS1
QSOP
MAX8537
MAX8539
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
BST1
DH1
LX1
ILIM1
PGND
DL1
GND
VL
V+
AVL
GND
COMP1
FB1
SS1
N.C.
SS2
FB2
COMP2
FREQ
EN1
EN2
POK2
DL2
POK1
ILIM2
LX2
DH2
BST2
QSOP
MAX8538
Pin Configurations

MAX8539EEI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Dual-Synchronous Buck Controller
Lifecycle:
New from this manufacturer.
Delivery:
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