RE46C190
DS22271A-page 16 2010 Microchip Technology Inc.
4.1 Calibration and Programming
Procedures
Eleven separate programming and test modes are
available for user customization. To enter these modes,
after power-up, TEST2 must be driven to V
DD
and held
at that level. The TEST input is then clocked to step
through the modes. FEED and IO are reconfigured to
become test mode inputs, while RLED, GLED and HB
become test mode outputs. The test mode functions for
each pin are outlined in Table 4-3.
When TEST2 is held at V
DD
, TEST becomes a tri-state
input with nominal input levels at V
SS
, V
DD
and V
BST
. A
TEST clock occurs whenever the TEST input switches
from V
SS
to V
BST
. The TEST Data column represents
the state of TEST when used as a data input, which
would be either V
SS
or V
DD
. The TEST pin can
therefore be used as both a clock, to change modes,
and a data input, once a mode is set. Other pin
functions are described in Section 4.2 “User
Selections”.
TABLE 4-3: TEST MODE FUNCTIONS
Mode
Description
TEST
Clock
TEST
Data
TEST2 FEED IO RLED GLED HB
V
IH
V
BST
V
DD
V
DD
V
BST
V
DD
—— —
V
IL
V
SS
V
SS
V
SS
V
SS
V
SS
—— —
T0 Photo Gain Factor
(2 bits)
0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
Integ Time (2 bits) 0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
IRED Current (2 bits) 0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
Low Battery Trip
(3 bits)
0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
LTD Enable (1 bit) 0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
Hush Option (1 bit) 0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
LB Hush Enable
(1 bit)
0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
EOL Enable (1 bit) 0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
Tone Select (1 bit) 0 ProgData V
DD
ProgCLK ProgEn 14 bits RLED GLED HB
T1 Norm Lim Set
(5 bits)
(
4
)
1 not used V
DD
CalCLK LatchLim
(
3
)
Gamp IntegOut SmkComp
(
1
)
T2 Hyst Lim Set
(5 bits)
(
4
)
2 not used V
DD
CalCLK LatchLim
(
3
)
Gamp IntegOut SmkComp
(
1
)
T3 Hush Lim Set
(5 bits)
(
4
)
3 not used V
DD
CalCLK LatchLim
(
3
)
Gamp IntegOut SmkComp
(
1
)
T4 Ch Test Lim Set
(5 bits)
(
4
)
4 not used V
DD
CalCLK LatchLim
(
3
)
Gamp IntegOut SmkComp
(
1
)
T5 LTD Baseline (5 bits) 5 not used V
DD
MeasEn ProgEn 25 bits Gamp IntegOut SmkComp
(
1
)
T6 Serial Read/Write 6 ProgData V
DD
ProgCLK ProgEn RLED GLED Serial Out
T7 Norm Lim Check 7 not used V
DD
MeasEn not used Gamp IntegOut SCMP
(
2
)
T8 Hyst Lim Check 8 not used V
DD
MeasEn not used Gamp IntegOut SCMP
(
2
)
T9 Hush Lim Check 9 not used V
DD
MeasEn not used Gamp IntegOut SCMP
(
2
)
T10 Ch Test Lim Check 10 not used V
DD
MeasEn not used Gamp IntegOut SCMP
(
2
)
T11 Horn Test 11 not used V
DD
FEED HornEn RLED GLED HB
Note 1: SmkComp (HB) – digital comparator output (high if Gamp < IntegOut; low if Gamp > IntegOut)
2: SCMP (HB) – digital output representing comparison of measurement value and associated limit. Signal is
valid only after MeasEn has been asserted and measurement has been made. (SCMP high if measured
value > limit; low if measured value < limit).
3: LatchLim (IO) – digital input used to latch present state of limits (Gamp level) for later storage. T1-T4 limits
are latched, but not stored until ProgEn is asserted in T5 mode.
4: Operating the circuit in this manner with nearly continuous IRED current for an extended period of time
may result in undesired or excessive heating of the part. The duration of this step should be minimized.
