PCA9673 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 September 2011 19 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
10.3 Differences between the PCA9673 and the PCF8575
The PCA9673 is a drop in replacement for the PCF8575 and can used without electrical
or software modifications, but there is a difference in interrupt output release timing during
the read operation.
Write operations are identical. At the completion of each 8-bit write sequence the data is
stored in its associated 8-bit write register at ACK or NACK. The first byte goes to P0n
while the second goes to P1n. Subsequent writes without a STOP wrap around to P0n
then P1n again. Any write will update both read registers and clear interrupts.
Read operations are identical. Both devices update the byte register with the pin data as
each 8-bit read is initiated, the very first read after an address cycle corresponds to ports
P0n while the second (even byte) corresponds to P1n and subsequent reads without a
STOP wrap around to P0n then P1n again.
During read operations, the PCA9673 interrupt output will be cleared in a byte-wise
fashion as each byte is read. Reading the first byte will clear any interrupts associated
with the P0n pins. This first byte read operation will have no effect on interrupts associated
with changes of state on the P1n pins. Interrupts associated with the P1n pins will be
cleared when the second byte is read. Reading the second byte has no effect on
interrupts associated with the changes of state on the P0x pins. The PCF8575 interrupt
output will clear after reading both bytes of data regardless of whether data was changed
in the first byte or the second byte or both bytes.
11. Limiting values
[1] Total package (maximum) output current is 600 mA.
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 0.5 +6 V
I
DD
supply current - 100 mA
I
SS
ground supply current - 600 mA
V
I
input voltage V
SS
0.5 5.5 V
I
I
input current - 20 mA
I
O
output current - 50
[1]
mA
P
tot
total power dissipation - 600 mW
P/out power dissipation per output - 200 mW
T
stg
storage temperature 65 +150 C
T
amb
ambient temperature operating 40 +85 C
PCA9673 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 September 2011 20 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
12. Static characteristics
[1] The power-on reset circuit resets the I
2
C-bus logic with V
DD
<V
POR
and set all I/Os to logic 1 (with current source to V
DD
).
Table 5. Static characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
V
DD
supply voltage 2.3 - 5.5 V
I
DD
supply current operating mode; no load;
V
I
=V
DD
or V
SS
; f
SCL
= 400 kHz
- 200 500 A
I
stb
standby current standby mode; no load;
V
I
=V
DD
or V
SS
-2.510A
V
POR
power-on reset voltage
[1]
-1.82.0V
Input SCL; input/output SDA
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
OL
LOW-level output current V
OL
=0.4V; V
DD
=2.3V 20 - - mA
V
OL
=0.4V; V
DD
=3.0V 25 - - mA
V
OL
=0.4V; V
DD
=4.5V 30 - - mA
I
L
leakage current V
I
=V
DD
or V
SS
1-+1A
C
i
input capacitance V
I
=V
SS
- 4 10 pF
I/Os; P00 to P07 and P10 to P17
I
OL
LOW-level output current V
OL
=0.5V; V
DD
=2.3V
[2]
12 27 - mA
V
OL
=0.5V; V
DD
=3.0V
[2]
17 35 - mA
V
OL
=0.5V; V
DD
=4.5V
[2]
25 42 - mA
I
OL(tot)
total LOW-level output current V
OL
=0.5V; V
DD
=4.5V
[2]
- - 400 mA
I
OH
HIGH-level output current V
OH
=V
SS
30 150 300 A
I
trt(pu)
transient boosted pull-up current V
OH
=V
SS
; see Figure 14 0.5 1.0 - mA
C
i
input capacitance
[3]
- 4 10 pF
C
o
output capacitance
[3]
- 4 10 pF
Interrupt INT
I
OL
LOW-level output current V
OL
=0.4V 6 - - mA
C
o
output capacitance - 3 5 pF
Input RESET
V
IL
LOW-level input voltage 0.5 - +0.8 V
V
IH
HIGH-level input voltage 2 - 5.5 V
I
LI
input leakage current 1-+1A
C
i
input capacitance - 3 5 pF
Inputs AD0, AD1
V
IL
LOW-level input voltage 0.5 - +0.3V
DD
V
V
IH
HIGH-level input voltage 0.7V
DD
-5.5V
I
LI
input leakage current 1-+1A
C
i
input capacitance - 3 5 pF
PCA9673 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 September 2011 21 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
[2] Each bit must be limited to a maximum of 25 mA and the total package limited to 400 mA due to internal busing limits.
[3] The value is not tested, but verified on sampling basis.
13. Dynamic characteristics
[1] t
VD;ACK
= time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] t
VD;DAT
= minimum time for SDA data out to be valid following SCL LOW.
Table 6. Dynamic characteristics
V
DD
= 2.3 V to 5.5 V; V
SS
=0V; T
amb
=
40
Cto+85
C; unless otherwise specified.
Symbol Parameter Conditions Standard mode
I
2
C-bus
Fast mode I
2
C-bus Fast-mode
Plus I
2
C-bus
Unit
Min Max Min Max Min Max
f
SCL
SCL clock frequency 0 100 0 400 0 1000 kHz
t
BUF
bus free time between a
STOP and START condition
4.7 - 1.3 - 0.5 - s
t
HD;STA
hold time (repeated) START
condition
4.0 - 0.6 - 0.26 - s
t
SU;STA
set-up time for a repeated
START condition
4.7 - 0.6 - 0.26 - s
t
SU;STO
set-up time for STOP
condition
4.0 - 0.6 - 0.26 - s
t
HD;DAT
data hold time 0 - 0 - 0 - ns
t
VD;ACK
data valid acknowledge time
[1]
0.3 3.45 0.1 0.9 0.05 0.45 s
t
VD;DAT
data valid time
[2]
300 - 50 - 50 450 ns
t
SU;DAT
data set-up time 250 - 100 - 50 - ns
t
LOW
LOW period of the SCL clock 4.7 - 1.3 - 0.5 - s
t
HIGH
HIGH period of the SCL
clock
4.0 - 0.6 - 0.26 - s
t
f
fall time of both SDA and
SCL signals
[4][5]
- 300 20 + 0.1C
b
[3]
300 - 120 ns
t
r
rise time of both SDA and
SCL signals
- 1000 20 + 0.1C
b
[3]
300 - 120 ns
t
SP
pulse width of spikes that
must be suppressed by the
input filter
[6]
-50 - 50-50ns
Port timing; C
L
100 pF (see Figure 14 and Figure 15)
t
v(Q)
data output valid time - 4 - 4 - 4 s
t
su(D)
data input set-up time 0 - 0 - 0 - s
t
h(D)
data input hold time 4 - 4 - 4 - s
Interrupt timing; C
L
100 pF (see Figure 14 and Figure 15)
t
v(D)
data input valid time - 4 - 4 - 4 s
t
d(rst)
reset delay time - 4 - 4 - 4 s
Reset timing (see Figure 25
)
t
w(rst)
reset pulse width 4 - 4 - 4 - ns
t
rec(rst)
reset recovery time 0 - 0 - 0 - ns
t
rst
reset time 100 - 100 - 100 - ns

PCA9673DB,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC I/O EXPANDER I2C 16B 24SSOP
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