UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 14 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
6.2.5 Int_Control register
Table 6. Int_Control register
Bit Symbol Access Power-on
default
Description
15:13 A2, A1, A0 R 010 register address
12 RO R/W 0 access status
0: register set to read/write
1: register set to read only
11 V1UIE R/W 0 V1 undervoltage interrupt enable
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
10 V2UIE R/W 0 V2 undervoltage interrupt enable
0: V2 undervoltage warning interrupts cannot be requested
1: V2 undervoltage warning interrupts can be requested
9 STBCL1 R/W 0 LIN1 standby control
0: When the SBC is in Normal mode (MC = 1x):
LIN1 is in Active mode. The wake-up flag (visible on RXDL1) is cleared
regardless of the value of V
BAT
.
When the SBC is in Standby/Sleep mode (MC = 0x):
LIN1 is in Off mode. Bus wake-up detection is disabled. LIN1 wake-up
interrupts cannot be requested.
1: LIN1 is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). LIN1 wake-up interrupts can be
requested.
8 STBCL2 R/W 0 LIN2 standby control
0: When the SBC is in Normal mode (MC = 1x):
LIN2 is in Active mode. The wake-up flag (visible on RXDL2) is cleared
regardless of the value of V
BAT
.
When the SBC is in Standby/Sleep mode (MC = 0x):
LIN2 is in Off mode. Bus wake-up detection is disabled. LIN2 wake-up
interrupts cannot be requested.
1: LIN2 is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). LIN2 wake-up interrupts can be
requested.
7:6 WIC1 R/W 00 wake-up interrupt 1 control
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
5:4 WIC2 R/W 00 wake-up interrupt 2 control
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges