UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 43 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
[1] . Variable t
bus(rec)(min)
is illustrated in the LIN timing diagram in Figure 20.
[2] Bus load conditions are: C
L
= 1 nF and R
L
=1kΩ; C
L
= 6.8 nF and R
L
= 660 Ω; C
L
= 10 nF and R
L
= 500 Ω.
[3] . Variable t
bus(rec)(max)
is illustrated in the LIN timing diagram in Figure 20.
[4] t
PD(RX)sym
=t
PD(RX)r
t
PD(RX)f
.
δ3 duty cycle 3 V
th(rec)RX(max)
= 0.778V
BAT
V
th(dom)RX(max)
= 0.616V
BAT
t
bit
= 96 μs; V
BAT
= 7 V to 18 V; LSC = 1
[1]
[2]
0.417 - -
V
th(rec)RX(max)
= 0.797V
BAT
V
th(dom)RX(max)
= 0.630V
BAT
t
bit
= 96 μs; V
BAT
= 5.5V to 7V; LSC=1
[1]
[2]
0.417 - -
δ4 duty cycle 4 V
th(rec)RX(min)
= 0.389V
BAT
V
th(dom)RX(min)
= 0.251V
BAT;
t
bit
= 96 μs
V
BAT
= 7.6 V to 18 V; LSC = 1
[2]
[3]
- - 0.590
V
th(rec)RX(min)
= 0.378V
BAT
V
th(dom)RX(min)
= 0.242V
BAT
; t
bit
= 96 μs
V
BAT
= 6.1 V to 7.6V; LSC = 1
[2]
[3]
- - 0.590
t
PD(RX)r
rising receiver propagation
delay
V
BAT
= 5.5 V to 18 V
R
RXDL1
= R
RXDL2
= 2.4 kΩ
C
RXDL1
= C
RXDL2
= 20 pF
--6 μs
t
PD(RX)f
falling receiver propagation
delay
V
BAT
= 5.5 V to 18 V
R
RXDL1
= R
RXDL2
= 2.4 kΩ
C
RXDL1
= C
RXDL2
= 20 pF
--6 μs
t
PD(RX)sym
receiver propagation delay
symmetry
V
BAT
= 5.5 V to 18 V
R
RXDL1
= R
RXDL2
= 2.4 kΩ
C
RXDL1
= C
RXDL2
= 20 pF
[4]
2-+2 μs
t
wake(busdom)min
minimum bus dominant
wake-up time
28 - 104 μs
t
to(dom)TXDL
TXDL dominant time-out
time
LIN online mode; V
TXDL
= 0 V 20 - 80 ms
Wake bias output; pin WBIAS
t
WBIASL
WBIAS LOW time 227 - 278 μs
t
cy
cycle time WBC = 1 58.1 - 71.2 ms
WBC = 0 14.5 - 17.8 ms
Watchdog
t
trig(wd)1
watchdog trigger time 1 Normal mode
watchdog Window mode only
[5]
0.45 ×
NWP
[6]
-0.555×
NWP
[6]
ms
t
trig(wd)2
watchdog trigger time 2 Normal, Standby and Sleep modes
watchdog Window mode only
[7]
0.9 ×
NWP
[6]
-1.11 ×
NWP
[6]
ms
Oscillator
f
osc
oscillator frequency 460.8 512 563.2 kHz
Table 11. Dynamic characteristics …continued
T
vj
=
40
°
C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
LIN1
= R
LIN2
=500
Ω
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all
voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
δ1 δ3,
t
bus rec()min()
2t
bit
×
-------------------------------
=
δ2 δ4,
t
bus rec()max()
2t
bit
×
--------------------------------
=
UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 44 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
[5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t
trig(wd)1
after the start of the watchdog
period (or in the first half of the watchdog period).
[6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4
); valid in watchdog
Window mode only.
[7] The watchdog will be reset if it is in window mode and is triggered at least t
trig(wd)1
, but not more than t
trig(wd)2
, after the start of the
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 17. Timing test circuit for CAN transceiver
Fig 18. CAN transceiver timing diagram
SBC
BAT
CANL
CANH
TXDC
R
CANH
R
CANL
RXDC
C
RXDC
GND
C
CANH
C
CANL
015aaa079
CANH
CANL
t
d(TXDC-busdom)
TXDC
V
O(dif)bus
RXDC
HIGH
HIGH
LOW
LOW
dominant
recessive
0.9 V
0.5 V
t
d(busdom-RXDC)
t
d(TXDC-busrec)
t
d(busrec-RXDC)
t
d(TXDCH-RXDCH)
t
d(TXDCL-RXDCL)
015aaa15
1
UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 45 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
Fig 19. Timing test circuit for LIN transceivers
SBC
BAT
LIN1
DLIN
TXDL1
R
LIN1
R
LIN2
C
LIN2
RXDL1
C
RXDL1
TXDL2
RXDL2
C
RXDL2
LIN2
GND
C
LIN1
015aaa081
Fig 20. Timing diagram LIN transceivers
015aaa131
V
TXDL1
/V
TXDL2
LIN1/LIN2
bus signal
V
BAT
t
bit
t
bus(rec)(min)
V
th(rec)RX(max)
thresholds of
receiving node A
V
th(dom)RX(max)
V
th(rec)RX(min)
V
th(dom)RX(min)
t
PD(RX)r
t
PD(RX)f
t
PD(RX)r
t
PD(RX)f
t
bus(rec)(max)
t
bit
t
bit
thresholds of
receiving node B
output of receiving
node A
V
RXDL1
/
V
RXDL2
output of receiving
node B
V
RXDL1
/
V
RXDL2
t
bus(dom)(max)
t
bus(dom)(min)

UJA1078ATW/5V0/WDJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1078ATW/HTSSOP32//5V0/WD/1/REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
Delivery:
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