UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 29 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
7. Limiting values
Table 8. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
x
voltage on pin x DC value
pins V1, V2 and INTN −0.3 7 V
pins TXDC, RXDC, EN, SDI, SDO, SCK, SCSN,
TXDL1, TXDL2, RXDL1, RXDL2, RSTN and
WDOFF
−0.3 V
V1
+ 0.3 V
pin VEXCC V
V1
− 0.3 V
V1
+ 0.35 V
pins WAKE1, WAKE2 and WBIAS; with respect to
any other pin
−58 +58 V
pin LIMP and BAT −0.3 +40 V
pin VEXCTRL −0.3 V
BAT
+ 0.3 V
pins CANH, CANL, SPLIT, LIN1 and LIN2; with
respect to any other pin
−58 +58 V
pin DLIN; with respect to any other pin V
BAT
− 0.3 +58 V
I
R(V1-BAT)
reverse current from
pin V1 to pin BAT
V
V1
≤ 5V
[1]
- 250 mA
I
DLIN
current on pin DLIN −65 0 mA
V
trt
transient voltage on pins
BAT: via reverse polarity diode/capacitor
CANL, CANH, SPLIT: coupling with two capacitors
on the bus lines
LIN1, LIN2: coupling via 1 nF capacitor
DLIN, WAKE1, WAKE2: via 1 kΩ series resistor
[2]
−150 +100 V
V
ESD
electrostatic
discharge voltage
IEC 61000-4-2
[3]
pins BAT with capacitor, CANH, CANL, LIN1 and
LIN2; via a series resistor on pins SPLIT, DLIN,
WAKE1 and WAKE2
[4]
−6+6kV
HBM
[5]
pins CANH, CANL, LIN1, LIN2, SPLIT, DLIN,
WAKE1, WAKE2
[6]
−8+8kV
pin BAT; referenced to ground −4+4kV
pin TEST2; referenced to pin BAT −1.25 +2 kV
pin TEST2; referenced to other reference pins −2+2kV
any other pin −2+2kV
MM
[7]
any pin −300 +300 V
CDM
[8]
corner pins −750 +750 V
any other pin −500 +500 V
