UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 37 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
I
LO
output leakage current V
SCSN
= V
V1
; V
O
= 0 V to V
V1
V
V1
= 2.97 V to 5.5 V
5- 5 μA
Reset output with clamping detection; pin RSTN
I
OH
HIGH-level output current V
RSTN
= 0.8V
V1
V
V1
= 2.97 V to 5.5 V
1500 - 100 μA
I
OL
LOW-level output current strong; V
RSTN
= 0.2V
V1
V
V1
= 2.97 V to 5.5 V
40 °C< T
vj
< 200 °C
4.9 - 40 mA
weak; V
RSTN
=0.8V
V1
V
V1
= 2.97 V to 5.5 V
40 °C< T
vj
< 200 °C
200 - 540 μA
V
OL
LOW-level output voltage V
V1
= 1 V to 5.5 V
pull-up resistor to V
V1
900 Ω
40 °C< T
vj
< 200 °C; V
BAT
< 28 V
0 - 0.2V
V1
V
V
V1
= 2.975 V to 5.5 V
pull-up resistor to V1 900 Ω;
40 °C< T
vj
<200 °C
0- 0.5V
V
OH
HIGH-level output voltage 40 °C< T
vj
< 200 °C0.8V
V1
-V
V1
+
0.3
V
V
th(sw)
switching threshold voltage V
V1
= 2.97 V to 5.5 V 0.3V
V1
-0.7V
V1
V
V
hys(i)
input hysteresis voltage V
V1
= 2.97 V to 5.5 V 100 - 900 mV
Interrupt output; pin INTN
I
OL
LOW-level output current V
OL
= 0.4 V 1.6 - 15 mA
Enable output; pin EN
I
OH
HIGH-level output current V
OH
= V
V1
0. 4 V
V
V1
= 2.97 V to 5.5 V
20 - 1.6 mA
I
OL
LOW-level output current V
OL
= 0.4 V; V
V1
= 2.97 V to 5.5 V 1.6 - 20 mA
V
OL
LOW-level output voltage I
OL
= 20 μA; V
V1
= 1.5 V - - 0.4 V
Watchdog off input; pin WDOFF
V
th(sw)
switching threshold voltage V
V1
= 2.97 V to 5.5 V 0.3V
V1
-0.7V
V1
V
V
hys(i)
input hysteresis voltage V
V1
= 2.97 V to 5.5 V 100 - 900 mV
R
pupd
pull-up/pull-down resistance V
V1
= 2.97 V to 5.5 V 5 10 20 kΩ
Wake input; pin WAKE1, WAKE2
V
th(sw)
switching threshold voltage 2 - 3.75 V
V
hys(i)
input hysteresis voltage 100 - 1000 mV
I
pu
pull-up current V
WAKE
= 0 V for t < t
wake
2- 0 μA
I
pd
pull-down current V
WAKE
= V
BAT
for t < t
wake
0- 2 μA
Limp home output; pin LIMP
I
O
output current V
LIMP
= 0.4 V; LHC = 1
T
vj
= 40 °C to 200 °C
0.8 - 8 mA
Wake bias output; pin WBIAS
I
O
output current V
WBIAS
= 1.4 V 1 - 7 mA
Table 10. Static characteristics …continued
T
vj
=
40
°
C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
LIN1
= R
LIN2
=500
Ω
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all
voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 38 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
CAN transmit data input; pin TXDC
V
th(sw)
switching threshold voltage V
V1
= 2.97 V to 5.5 V 0.3V
V1
-0.7V
V1
V
V
hys(i)
input hysteresis voltage V
V1
= 2.97 V to 5.5 V 100 - 900 mV
R
pu
pull-up resistance 4 12 25 kΩ
CAN receive data output; pin RXDC
I
OH
HIGH-level output current CAN Active mode
V
RXDC
= V
V1
0.4 V
20 - 1.5 mA
I
OL
LOW-level output current V
RXDC
= 0.4 V 1.6 - 20 mA
R
pu
pull-up resistance MC = 00; Standby mode 4 12 25 kΩ
High-speed CAN bus lines; pins CANH and CANL
V
O(dom)
dominant output voltage CAN Active mode
V
V2
= 4.5 V to 5.5 V; V
TXDC
= 0 V
R
(CANH-CANL)
= 60 Ω
pin CANH 2.75 3.5 4.5 V
pin CANL 0.5 1.5 2.25 V
V
dom(TX)sym
transmitter dominant voltage
symmetry
V
dom(TX)sym
= V
V2
V
CANH
V
CANL
R
(CANH-CANL)
= 60 Ω
400 - +400 mV
V
O(dif)bus
bus differential output
voltage
CAN Active mode (dominant)
V
V2
= 4.75 V to 5.25 V; V
TXDC
= 0 V
R
(CANH-CANL)
= 45 Ω to 65 Ω
1.5 - 3.0 V
CAN Active mode (recessive)
V
V2
= 4.5 V to 5.5 V; V
TXDC
= V
V1
R
(CANH-CANL)
= no load
50 0 +50 mV
V
O(rec)
recessive output voltage CAN Active mode; V
V2
= 4.5 V to 5.5 V
V
TXDC
= V
V1
R
(CANH-CANL)
= no load
20.5V
V2
3V
CAN Lowpower/Off mode
R
(CANH-CANL)
= no load
0.1 - +0.1 V
I
O(dom)
dominant output current CAN Active mode
V
TXDC
=0V; V
V2
= 5 V
pin CANH; V
CANH
=0V 100 70 40 mA
pin CANL; V
CANL
= 40 V 40 70 100 mA
I
O(rec)
recessive output current V
CANL
= V
CANH
= 27 V to +32 V
V
TXDC
= V
V1
; V
V2
= 4.5 V to 5.5 V
3- +3 mA
V
th(RX)dif
differential receiver
threshold voltage
CAN Active mode
V
V2
= 4.5 V to 5.5 V
30 V < V
CANH
< +30 V
30 V < V
CANL
< +30 V
0.5 0.7 0.9 V
CAN Lowpower mode
12 V < V
CANH
< +12 V
12 V < V
CANL
< +12 V
0.4 0.7 1.15 V
Table 10. Static characteristics
…continued
T
vj
=
40
°
C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
LIN1
= R
LIN2
=500
Ω
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all
voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
UJA1078A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 28 January 2011 39 of 54
NXP Semiconductors
UJA1078A
High-speed CAN/dual LIN core system basis chip
V
hys(RX)dif
differential receiver
hysteresis voltage
CAN Active mode
V
V2
= 4.5 V to 5.5 V
30 V < V
CANH
< +30 V
30 V < V
CANL
< +30 V
40 120 400 mV
R
i(cm)
common-mode input
resistance
CAN Active mode; V
V2
= 5 V
V
CANH
= V
CANL
= 5 V
91528kΩ
ΔR
i
input resistance deviation CAN Active mode; V
V2
= 5 V
V
CANH
= V
CANL
=5V
1- +1 %
R
i(dif)
differential input resistance CAN Active mode; V
V2
= 5.5 V
V
CANH
= V
CANL
= 35 V to +35 V
19 30 52 kΩ
C
i(cm)
common-mode input
capacitance
CAN Active mode; not tested - - 20 pF
C
i(dif)
differential input capacitance CAN Active mode; not tested - - 10 pF
I
LI
input leakage current V
BAT
= 0 V; V
V2
= 0 V
V
CANH
= V
CANL
=5V
5 - +5 μA
CAN bus common mode stabilization output; pin SPLIT
V
O
output voltage CAN Active mode
V
V2
= 4.5 V to 5.5 V
I
SPLIT
= 500 μA to 500 μA
0.3V
V2
0.5V
V2
0.7V
V2
V
CAN Active mode
V
V2
= 4.5 V to 5.5 V; R
L
1MΩ
0.45 ×
V
V2
0.5 ×
V
V2
0.55 ×
V
V2
V
I
L
leakage current CAN Lowpower/Off mode or Active
mode with V
V2
< 4.5 V
V
SPLIT
= 30 V to + 30 V
5- +5 μA
LIN transmit data input; pin TXDL1, TXDL2
V
th(sw)
switching threshold voltage V
V1
= 2.97 V to 5.5 V 0.3V
V1
-0.7V
V1
V
V
hys(i)
input hysteresis voltage V
V1
= 2.97 V to 5.5 V 100 - 900 mV
R
pu
pull-up resistance 4 12 25 kΩ
LIN receive data output; pin RXDL1, RXDL2
I
OH
HIGH-level output current LIN Active mode
V
RXDL1
= V
RXDL2
= V
V1
0.4 V
20 - 1.5 mA
I
OL
LOW-level output current V
RXDL1
= V
RXDL2
= 0.4 V 1.6 - 20 mA
R
pu
pull-up resistance MC = 00; Standby mode 4 12 25 kΩ
LIN bus line; pin LIN1, LIN2
I
BUS_LIM
current limitation for driver
dominant state
LIN Active mode
V
BAT
= V
LIN1
=V
LIN2
= 18 V
V
TXDL1
= V
TXDL2
= 0 V
40 - 100 mA
I
BUS_PAS_rec
receiver recessive input
leakage current
V
LIN1
=V
LIN2
= 28 V
V
BAT
= 5.5 V; V
TXDL1
= V
TXDL2
= V
V1
[1]
--2 μA
I
BUS_PAS_dom
receiver dominant input
leakage current including
pull-up resistor
V
TXDL1
= V
TXDL2
= V
V1
V
LIN1
=V
LIN2
= 0 V; V
BAT
= 14 V
10 - +10 μA
I
L(log)
loss of ground leakage
current
V
BAT
= V
GND
=28V; V
LIN1
=V
LIN2
= 0 V 100 - 10 μA
Table 10. Static characteristics …continued
T
vj
=
40
°
C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; V
BAT
> V
V2
; R
LIN1
= R
LIN2
=500
Ω
; R
(CANH-CANL)
= 45
Ω
to 65
Ω
; all
voltages are defined with respect to ground; positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

UJA1078ATW/5V0/WDJ

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC UJA1078ATW/HTSSOP32//5V0/WD/1/REEL 13 Q1 NDP
Lifecycle:
New from this manufacturer.
Delivery:
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