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TISP4219H3BJR

P1-P3P4-P6P7-P9P10-P12P13-P13
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
TISP4125H3BJ/TISP4219H3BJ,
TISP4125M3BJ/TISP4219M3BJ
LCAS RING AND TIP PROTECTION PAIRS
BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
Description
Customized Voltage for LCAS Protection
Battery-Backed Ringing ............................................. 87 V rms
Ground-Backed Ringing ........................................... 101 V rms
Low Differential Capacitance ................................. 39 pF max.
.................................................... UL Recognized Components
Rated for International Surge Wave Shapes
These protector pairs have been formulated to limit the peak voltages on the line terminals of the ‘7581/2/3 LCAS (Line Card Access Switches)
type devices. An LCAS may also be referred to as a Solid State Relay, SSR, i.e. a replacement of the conventional electro-mechanical relay.
Overvoltages are normally caused by a.c. power system or lightning flash disturbances which are induced or conducted on to the telephone
line. These overvoltages are initially clipped by protector breakdown clamping until the voltage rises to the breakover level, which causes the
device to crowbar into a low-voltage on state. This low-voltage on state causes the current resulting from the overvoltage to be safely diverted
through the device. For negative surges, the high crowbar holding current helps prevent d.c. latchup with the SLIC current, as the surge current
subsides.
Each protector consists of a symmetrical voltage-triggered bidirectional thyristor. They are guaranteed to voltage limit and withstand the listed
international lightning surges in both polarities.
How to Order
Device Symbol
SMBJ Package (Top View)
Device
V
DRM
V
V
(BO)
V
LCAS
TERMINAL
‘4125 100 125 TIP
‘4219 180 219 RING
Wave Shape Standard
I
TSP
A
H3
SERIES
M3
SERIES
2/10 µs GR-1089-CORE 500 300
8/20 µs IEC 61000-4-5 300 220
10/160 µs FCC Part 68 250 120
10/700 µs ITU-T K.20/21/45 200 100
10/560 µs FCC Part 68 160 75
10/1000 µs GR-1089-CORE 100 50
12
T(A)
R(B)
MDXXBGE
T
R
SD4XAA
Terminals T and R correspond to the
alternative line designators of A and B
*RoHS Directive 2002/95/EC Jan 27 2003 including Annex
Device Package Carrier
TISP4125H3BJ
BJ (J-Bend DO-214AA/SMB) Embossed Tape Reeled
TISP4219H3BJ
TISP4125M3BJ
TISP4219M3BJ
TISP4125H3BJR-S
TISP4219H3BJR-S
TISP4125M3BJR-S
TISP4219M3BJR-S
Order As
*
R
o
H
S
C
O
M
P
L
I
A
N
T
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
Absolute Maximum Ratings, T
A
= 25 °C (Unless Otherwise Noted)
TISP4xxxH3/M3BJ Series for LCAS Protection
Recommended Operating Conditions
Component Condition Min Typ Max Unit
R
S
Series current limiting
resistor
GR-1089-CORE first-level surge survival 0
Ω
GR-1089-CORE first-level and second-level surge survival 0 Ω
K.20, K.21 and K.45 coordination pass with a 400 V primary
protector
6
Ω
V
RING
AC ringing voltage
Figure 12, V
BAT
= -48 V ±2.5 V,
R1= R2 = 300
Ω, 0 °C < T
A
< +85 °C
Battery-backed 87 V rms
V rms
Ground-backed 101
TISP4125H3BJ & TISP4219H3BJ
Rating Symbol Value Unit
Repetitive peak off-state voltage, (see Note 1)
‘4125
‘4219
V
DRM
±100
±180
V
Non-repetitive peak on-state pulse current (see Notes 2 and 3)
I
TSP
A
2/10 µs (GR-1089-CORE, 2/10 µs voltage wave shape) 500
8/20 µs (IEC 61000-4-5, 1.2/50 µs voltage, 8/20 current combination wave generator) 300
10/160 µs (F CC Part 68, 10/160 µs voltage wave shape) 250
5/200 µs (VDE 0433, 10/700 µs voltage wave shape) 220
0.2/310 µs (I3124, 0.5/700 µs voltage wave shape) 200
5/310 µs (ITU-T K.20/21, 10/700 µs voltage wave shape) 200
5/310 µs (FTZ R12, 10/700 µs voltage wave shape) 200
10/560 µs (F CC Part 68, 10/560 µs voltage wave shape) 160
10/1000 µs (GR-1089-CORE, 10/1000 µs voltage wave shape) 100
Non-repetitive peak on-state current (see Notes 2, 3 and 4)
I
TSM
55
60
2.1
A
20 ms (50 Hz) full sine wave
16.7 ms (60 Hz) full sine wave
1000 s 50 Hz/60 Hz a.c.
Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 200 A di
T
/dt 400 A/µs
Junction temperature T
J
-40 to +150 °C
Storage temperature range T
stg
-65 to +150 °C
NOTES: 1. See Applications Information for voltage values at lower temperatures.
2. Initially, the TISP4xxxH3BJ must be in thermal equilibrium with T
J
=25°C.
3. The surge may be repeated after the TISP4xxxH3BJ returns to its initial conditions.
4. EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring
track widths. See Figure 10 for the current ratings at other durations. Derate current values at -0.61 %/°C for ambient
temperatures above 25 °C.
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Electrical Characteristics, TISP4xxxH3, T
A
= 25 °C (Unless Otherwise Noted)
Thermal Characteristics
Parameter Test Conditions Min Typ Max Unit
I
DRM
Repetitive peak off-
state current
V
D
= V
DRM
T
A
= 25 °C
T
A
= 85 °C
±5
±10
µA
V
(BO)
Breakover voltage dv/dt = ±250 V/ms, R
SOURCE
= 300
Ω
‘4125
‘4219
±125
±219
V
V
(BO)
Impulse breakover
voltage
dv/dt
≤
±1000 V/µs, Linear voltage ramp,
Maximum ramp value = ±500 V
di/dt = ±20 A/µs, Linear current ramp,
Maximum ramp value = ±10 A
‘4125
‘4219
±134
±229
V
I
(BO)
Breakover current dv/dt = ±250 V/ms, R
SOURCE
= 300 Ω ±0.15 ±0.6 A
V
T
On-state voltage I
T
= ±5A, t
W
= 100 µs ±3V
I
H
Holding current I
T
= ±5A, di/dt=+/-30mA/ms ±0.15 ±0.6 A
dv/dt
Critical rate of rise of
off-state voltage
Linear voltage ramp, Maximum ramp value < 0.85V
DRM
±5 kV/µs
I
D
Off-state current V
D
= ±50 V T
A
= 85 °C ±10 µA
C
off
Off-state capacitance
f=1MHz, V
d
=1V rms, V
D
=0,
f=1MHz, V
d
=1V rms, V
D
=-1V
f=1MHz, V
d
=1V rms, V
D
=-2V
f=1MHz, V
d
=1V rms, V
D
=-50V
f=1MHz, V
d
=1V rms, V
D
= -100 V
(see Note 5)
80
71
65
30
23
90
79
74
35
28
pF
NOTE 5: To avoid possible voltage clipping, the ‘4125 is tested with V
D
=-98V.
Parameter Test Conditions Min Typ Max Unit
R
θJA
Junction to free air thermal resistance
EIA/JESD51-3 PCB, I
T
= I
TSM(1000)
,
T
A
= 25 °C, (see Note 6)
113
°C/W
265 mm x 210 mm populated line card,
4-layer PCB, I
T
= I
TSM(1000)
, T
A
= 25 °C
50
NOTE 6: EIA/JESD51-2 environment and the PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
P1-P3P4-P6P7-P9P10-P12P13-P13

TISP4219H3BJR

Mfr. #:
Buy TISP4219H3BJR
Manufacturer:
Bourns
Description:
Thyristor Surge Protection Devices (TSPD)
Lifecycle:
New from this manufacturer.
Delivery:
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