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TISP4219H3BJR

P1-P3P4-P6P7-P9P10-P12P13-P13
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Absolute Maximum Ratings, T
A
= 25 °C (Unless Otherwise Noted)
Rating Symbol Value Unit
Repetitive peak off-state voltage, (see Note 7)
‘4125
‘4219
V
DRM
±100
±180
V
Non-repetitive peak on-state pulse current (see Notes 8 and 9)
I
TSP
A
2/10 µs (GR-1089-CORE, 2/10 µs voltage wave shape) 300
8/20 µs (IEC 61000-4-5, 1.2/50 µs voltage, 8/20 current combination wave generator) 220
10/160 µs (F CC Part 68, 10/160 µs voltage wave shape) 120
5/200 µs (VDE 0433, 10/700 µs voltage wave shape) 110
0.2/310 µs (I3124, 0.5/700 µs voltage wave shape) 100
5/310 µs (ITU-T K.20/21, 10/700 µs voltage wave shape) 100
5/310 µs (FTZ R12, 10/700 µs voltage wave shape) 100
10/560 µs (F CC Part 68, 10/560 µs voltage wave shape) 75
10/1000 µs (GR-1089-CORE, 10/1000 µs voltage wave shape) 50
Non-repetitive peak on-state current (see Notes 8, 9 and 10)
I
TSM
30
32
2.1
A
20 ms (50 Hz) full sine wave
16.7 ms (60 Hz) full sine wave
1000 s 50 Hz/60 Hz a.c.
Initial rate of rise of on-state current, Exponential current ramp, Maximum ramp value < 200 A di
T
/dt 300 A/µs
Junction temperature T
J
-40 to +150 °C
Storage temperature range T
stg
-65 to +150 °C
NOTES: 7. See Applications Information for voltage values at lower temperatures.
8. Initially, the TISP4xxxM3BJ must be in thermal equilibrium with T
J
=25°C.
9. The surge may be repeated after the TISP4xxxM3BJ returns to its initial conditions.
10.EIA/JESD51-2 environment and EIA/JESD51-3 PCB with standard footprint dimensions connected with 5 A rated printed wiring
track widths. See Figure 11 for the current ratings at other durations. Derate current values at -0.61 %/°C for ambient
temperatures above 25 °C.
Recommended Operating Conditions
Component Condition Min Typ Max Unit
R
S
Series current limiting
resistor
GR-1089-CORE first-level surge survival 10
Ω
GR-1089-CORE first-level and second-level surge survival 12 Ω
K.20, K.21 and K.45 coordination pass with a 400 V primary
protector
6
Ω
V
RING
AC ringing voltage
Figure 12, V
BAT
= -48 V ±2.5 V,
R1= R2 = 300
Ω, 0 °C < T
A
< +85 °C
Battery-backed 87 V rms
V rms
Ground-backed 101
TISP4125M3BJ & TISP4219M3BJ
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Electrical Characteristics, TISP4xxxM3, T
A
= 25 °C (Unless Otherwise Noted)
Parameter Test Conditions Min Typ Max Unit
I
DRM
Repetitive peak off-
state current
V
D
= V
DRM
T
A
= 25 °C
T
A
= 85 °C
±5
±10
µA
V
(BO)
Breakover voltage dv/dt = ±250 V/ms, R
SOURCE
= 300
Ω
‘4125
‘4219
±125
±219
V
V
(BO)
Impulse breakover
voltage
dv/dt
≤
±1000 V/µs, Linear voltage ramp,
Maximum ramp value = ±500 V
di/dt = ±20 A/µs, Linear current ramp,
Maximum ramp value = ±10 A
‘4125
‘4219
±132
±226
V
I
(BO)
Breakover current dv/dt = ±250 V/ms, R
SOURCE
= 300 Ω ±0.15 ±0.6 A
V
T
On-state voltage I
T
= ±5A, t
W
= 100 µs ±3V
I
H
Holding current I
T
= ±5A, di/dt=+/-30mA/ms ±0.15 ±0.6 A
dv/dt
Critical rate of rise of
off-state voltage
Linear voltage ramp, Maximum ramp value < 0.85V
DRM
±5 kV/µs
I
D
Off-state current V
D
= ±50 V T
A
= 85 °C ±10 µA
C
off
Off-state capacitance
f=1MHz, V
d
=1V rms, V
D
=0,
f=1MHz, V
d
=1V rms, V
D
=-1V
f=1MHz, V
d
=1V rms, V
D
=-2V
f=1MHz, V
d
=1V rms, V
D
=-50V
f=1MHz, V
d
=1V rms, V
D
= -100 V
(see Note 11)
62
56
52
26
21
74
67
62
31
25
pF
NOTE 11: To avoid possible voltage clipping, the ‘4125 is tested with V
D
=-98V.
Thermal Characteristics
Parameter Test Conditions Min Typ Max Unit
R
θJA
Junction to free air thermal resistance
EIA/JESD51-3 PCB, I
T
= I
TSM(1000)
,
T
A
= 25 °C, (see Note 12)
115
°C/W
265 mm x 210 mm populated line card,
4-layer PCB, I
T
= I
TSM(1000)
, T
A
= 25 °C
52
NOTE 12: EIA/JESD51-2 environment and the PCB has standard footprint dimensions connected with 5 A rated printed wiring track widths.
JUNE 2001 – REVISED JANUARY 2007
Specifications are subject to change without notice.
Customers should verify actual device performance in their specific applications.
TISP4xxxH3/M3BJ Series for LCAS Protection
Parameter Measurement Information
Figure 1. Voltage-Current Characteristic for T and R Terminals
All Measurements are Referenced to the R Terminal
-v
V
DRM
I
DRM
V
D
I
H
I
T
V
T
I
TSM
I
TSP
V
(BO)
I
(BO)
I
D
Quadrant I
I
Switching
Characteristic
+v
+i
V
(BO)
I
(BO)
V
D
I
D
I
H
I
T
V
T
I
TSM
I
TSP
-i
Quadrant III
Switching
Characteristic
PMXXAAB
V
DRM
I
DRM
P1-P3P4-P6P7-P9P10-P12P13-P13

TISP4219H3BJR

Mfr. #:
Buy TISP4219H3BJR
Manufacturer:
Bourns
Description:
Thyristor Surge Protection Devices (TSPD)
Lifecycle:
New from this manufacturer.
Delivery:
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