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AD7858LARZ

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REV. B
–10–
AD7858/AD7858L
CONTROL REGISTER
The arrangement of the Control Register is shown below. The control register is a write only register and contains 14 bits of data.
The control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are de-
scribed below. The power-up status of all bits is 0.
MSB
SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0 RDSLT1
RDSLT0 2/3 MODE CONVST CALMD CALSLT1 CALSLT0 STCAL
LSB
CONTROL REGISTER BIT FUNCTION DESCRIPTION
Bit Mnemonic Comment
13 SGL/DIFF A 0 in this bit position configures the input channels in pseudo-differential mode. A 1 in this bit position
configures the input channels in single-ended mode (see Table III).
12 CH2 These three bits are used to select the channel on which the conversion is performed. The channels can
11 CH1 be configured as eight single-ended channels or four pseudo-differential channels. The default selection
10 CH0 is AIN1 for the positive input and AIN2 for the negative input (see Table III for channel selection).
9 PMGT1 Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
8 PMGT0 Power-Down Modes (see Power-Down section for more details).
7 RDSLT1 Theses two bits determine which register is addressed for the read operations (see Table II).
6 RDSLT0
52/3 MODE Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,
Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using the Two-Wire Interface Mode, this bit needs to be set to
1 in every write cycle.
4 CONVST Conversion Start Bit. A logic one in this bit position starts a single conversion, and this bit is automati-
cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration
(see Calibration section.)
3 CALMD Calibration Mode Bit. A 0 here selects self-calibration, and a 1 selects a system calibration (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. These bits have two functions.
1 CALSLT0 With the STCAL bit set to 1 the CALSLT1 and CALSLT0 bits determine the type of calibration per
0 STCAL formed by the part (see Table IV). The STCAL bit is automatically reset to 0 at the end of calibration.
With the STCAL bit set to 0 the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on the Calibration Registers for more details).
AD7858/AD7858L
REV. B
–11–
Table III. Channel Selection
SGL/DIFF CH2 CH1 CH0 AIN(+)* AIN(–)*
0 0 0 0 AIN
1
AIN
2
0 0 0 1 AIN
3
AIN
4
0 0 1 0 AIN
5
AIN
6
0 0 1 1 AIN
7
AIN
8
0 1 0 0 AIN
2
AIN
1
0 1 0 1 AIN
4
AIN
3
0 1 1 0 AIN
6
AIN
5
0 1 1 1 AIN
8
AIN
7
1 0 0 0 AIN
1
AGND
1 0 0 1 AIN
3
AGND
1 0 1 0 AIN
5
AGND
1 0 1 1 AIN
7
AGND
1 1 0 0 AIN
2
AGND
1 1 0 1 AIN
4
AGND
1 1 1 0 AIN
6
AGND
1 1 1 1 AIN
8
AGND
*AIN(+) refers to the positive input seen by the AD7858/AD7858L sample and hold circuit,
*AIN(–) refers to the negative input seen by the AD7858/AD7858L sample and hold circuit.
Table IV. Calibration Selection
CALMD CALSLT1 CALSLT0 Calibration Type
000A Full Internal Calibration is initiated where the Internal DAC is calibrated
followed by the Internal Gain Error, and finally the Internal Offset Error is
calibrated out. This is the default setting.
0 0 1 Here the Internal Gain Error is calibrated out followed by the Internal Offset
Error calibrated out.
0 1 0 This calibrates out the Internal Offset Error only.
0 1 1 This calibrates out the Internal Gain Error only.
100A Full System Calibration is initiated here where first the Internal DAC is
calibrated followed by the System Gain Error, and finally the System Offset
Error is calibrated out.
1 0 1 Here the System Gain Error is calibrated out followed by the System Offset
Error.
1 1 0 This calibrates out the System Offset Error only.
1 1 1 This calibrates out the System Gain Error only.
REV. B
–12–
AD7858/AD7858L
MSB
ZERO BUSY SGL/DIFF CH2 CH1 CH0 PMGT1 PMGT0
RDSLT1 RDSLT0 2/3 MODE X CALMD CALSLT1 CALSLT0 STCAL
LSB
STATUS REGISTER BIT FUNCTION DESCRIPTION
Bit Mnemonic Comment
15 ZERO This bit is always 0.
14 BUSY Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion
or calibration in progress. When this bit is 0, there is no conversion or calibration in progress.
13 SGL/DIFF These four bits indicate the channel selected for conversion (see Table III).
12 CH2
11 CH1
10 CH0
9 PMGT1 Power management bits. These bits along with the SLEEP pin will indicate if the part is in a
8 PMGT0 power-down mode or not. See Table VI for description.
7 RDSLT1 Both of these bits are always 1, indicating it is the status register being read (see Table II).
6 RDSLT0
52/3 MODE Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at
1, the device is in Interface Mode 1. This bit is reset to 0 after every read cycle.
4X Don’t care bit.
3 CALMD Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected, and a 1 in this bit
indicates a system calibration is selected (see Table IV).
2 CALSLT1 Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a
1 CALSLT0 calibration is in progress and as a 0 if there is no calibration in progress. The CALSLT1 and
0 STCAL CALSLT0 bits indicate which of the calibration registers are addressed for reading and writing
(see section on the Calibration Registers for more details).
STATUS REGISTER
The arrangement of the Status Register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the bits
in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
Figure 6. Flowchart for Reading the Status Register
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AD7858LARZ

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Buy AD7858LARZ
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit
Lifecycle:
New from this manufacturer.
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