AD7858LARZ Datasheet AD7858BRZ, AD7858ARZ, AD7858LARZ | P13-P15

AD7858/AD7858L

REV. B

–13–

CALIBRATION REGISTERS

The AD7858/AD7858L has 10 calibration registers in all, eight for the DAC, one for the offset, and one for gain. Data can be written

to or read from all 10 calibration registers. In self- and system calibration the part automatically modifies the calibration registers; only if the

user needs to modify the calibration registers should an attempt be made to read from and write to the calibration registers.

Addressing the Calibration Registers

The calibration selection bits in the control register CALSLT1 and CALSLT0 determine which of the calibration registers are ad-

dressed (see Table V). The addressing applies to both the read and write operations for the calibration registers. The user should not

attempt to read from and write to the calibration registers at the same time.

Table V. Calibration Register Addressing

CALSLT1 CALSLT0 Comment

0 0 This combination addresses the Gain (1), Offset (1) and DAC Registers (8). Ten registers in total.

0 1 This combination addresses the Gain (1) and Offset (1) Registers. Two registers in total.

1 0 This combination addresses the Offset Register. One register in total.

1 1 This combination addresses the Gain Register. One register in total.

Writing to/Reading from the Calibration Registers

For writing to the calibration registers a write to the control

For reading from the calibration registers a write to the control

but also to set the RDSLT1 and RDSLT0 bits to 10 (this ad-

dresses the calibration registers for reading). The calibration

the CALSLT1 and CALSLT0 bits, or upon completion of all

the calibration register write/read operations. When reset it

points to the first calibration register in the selected write/read

sequence. The calibration register pointer will point to the gain

calibration register upon reset in all but one case, this case being

where the offset calibration register is selected on its own

(CALSLT1 = 1, CALSLT0 = 0). Where more than one calibra-

tion register is being accessed the calibration register pointer will

be automatically incremented after each calibration register

write/read operation. The order in which the 10 calibration

registers are arranged is shown in Figure 7. The user may abort

at any time before all the calibration register write/read opera-

tions are completed, and the next control register write opera-

tion will reset the calibration register pointer. The flow chart in

Figure 8 shows the sequence for writing to the calibration regis-

ters and Figure 9 for reading.

CAL REGISTER

ADDRESS POINTER

GAIN REGISTER

OFFSET REGISTER

DAC 1ST MSB REGISTER

DAC 8TH MSB REGISTER

(1)

(2)

(3)

(10)

CALIBRATION REGISTERS

CALIBRATION REGISTER

ADDRESS POINTER

POSITION IS DETERMINED

BY THE NUMBER OF

CALIBRATION REGISTERS

ADDRESSED AND THE

NUMBER OF READ/WRITE

OPERATIONS

Figure 7. Calibration Register Arrangements

When reading from the calibration registers there will always be

two leading zeros for each of the registers. When operating in

Serial Interface Mode 1 the read operations to the calibration

registers cannot be aborted. The full number of read operations

must be completed (see section on Serial Interface Mode 1

Timing for more detail).

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0

AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

WRITE TO CAL REGISTER

(ADDR1 = 1, ADDR0 = 0)

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

WRITE

OPERATION

ABORT

FINISHED

YES

Figure 8. Flowchart for Writing to the Calibration Registers

REV. B

–14–

AD7858/AD7858L

START

WRITE TO CONTROL REGISTER SETTING STCAL = 0, RDSLT1 = 1,

RDSLT0 = 0, AND CALSLT1, CALSLT0 = 00, 01, 10, 11

CAL REGISTER POINTER IS

AUTOMATICALLY RESET

READ CAL REGISTER

CAL REGISTER POINTER IS

AUTOMATICALLY INCREMENTED

LAST

READ

OPERATION

ABORT

FINISHED

YES

Figure 9. Flowchart for Reading from the Calibration

Registers

Adjusting the Offset Calibration Register

The offset calibration register contains 16 bits, two leading zeros,

and 14 data bits. By changing the contents of the offset register

different amounts of offset on the analog input signal can be

compensated for. Increasing the number in the offset calibration

signal, and decreasing the number in the offset calibration regis-

ter compensates for positive offset on the analog input signal.

The default value of the offset calibration register is 0010 0000

0000 0000 approximately. This is not an exact value, but the

value in the offset register should be close to this value. Each of

the 14 data bits in the offset register is binary weighted; the

MSB has a weighting of 5% of the reference voltage, the MSB-1

has a weighting of 2.5%, the MSB-2 has a weighting of 1.25%,

and so on down to the LSB which has a weighting of 0.0006%.

This gives a resolution of ±0.0006% of V

REF

approximately.

More accurately the resolution is ± (0.05 × V

REF

)/2

volts =

±0.015 mV, with a 2.5 V reference. The maximum offset that

can be compensated for is ±5% of the reference voltage, which

equates to ±125 mV with a 2.5 V reference and ±250 mV with

a 5 V reference.

Q. If a +20 mV offset is present in the analog input signal and the

reference voltage is 2.5 V what code needs to be written to the

offset register to compensate for the offset?

A. 2.5 V reference implies that the resolution in the offset regis-

ter is 5% × 2.5 V/2

= 0.015 mV. +20 mV/0.015 mV =

1310.72; rounding to the nearest number gives 1311. In

binary terms this is 0101 0001 1111. Therefore, decrease the

offset register by 0101 0001 1111.

This method of compensating for offset in the analog input

signal allows for fine tuning the offset compensation. If the

offset on the analog input signal is known, there will be no need

to apply the offset voltage to the analog input pins and do a

system calibration. The offset compensation can take place in

software.

Adjusting the Gain Calibration Register

The gain calibration register contains 16 bits, two leading 0s

and 14 data bits. The data bits are binary weighted as in the

offset calibration register. The gain register value is effectively

multiplied by the analog input to scale the conversion result

over the full range. Increasing the gain register compensates for

a smaller analog input range and decreasing the gain register

compensates for a larger input range. The maximum analog

input range that the gain register can compensate for is 1.025

times the reference voltage, and the minimum input range is

0.975 times the reference voltage.

AD7858/AD7858L

REV. B

–15–

CIRCUIT INFORMATION

The AD7858/AD7858L is a fast, 12-bit single supply A/D con-

verter. The part requires an external 4 MHz/1.8 MHz master

clock (CLKIN), two C

REF

capacitors, a CONVST signal to start

conversion, and power supply decoupling capacitors. The part

provides the user with track/hold, on-chip reference, calibration

features, A/D converter, and serial interface logic functions on a

single chip. The A/D converter section of the AD7858/AD7858L

consists of a conventional successive-approximation converter

based around a capacitor DAC. The AD7858/AD7858L accepts

an analog input range of 0 to +V

where the reference can be

tied to V

. The reference input to the part is buffered on-chip.

A major advantage of the AD7858/AD7858L is that a conversion

can be initiated in software as well as applying a signal to the

CONVST pin. Another innovative feature of the AD7858/

AD7858L is self-calibration on power-up, which is initiated

having a capacitor from the CAL pin to AGND, to give superior

dc accuracy. See Automatic Calibration on Power-Up section.

The part is available in a 24-pin SSOP package and this offers

the user considerable space-saving advantages over alternative

solutions. The AD7858L version typically consumes only

5.5 mW making it ideal for battery-powered applications.

CONVERTER DETAILS

The master clock for the part must be applied to the CLKIN

pin. Conversion is initiated on the AD7858/AD7858L by pulsing

the CONVST input or by writing to the control register and

setting the CONVST bit to 1. On the rising edge of CONVST

(or at the end of the control register write operation), the on-

chip track/hold goes from track to hold mode. The falling edge

of the CLKIN signal that follows the rising edge of the CONVST

signal initiates the conversion, provided the rising edge of

CONVST occurs at least 10 ns typically before this CLKIN

edge. The conversion cycle will take 16.5 CLKIN periods from

this CLKIN falling edge. If the 10 ns setup time is not met, the

conversion will take 17.5 CLKIN periods. The maximum speci-

fied conversion time is 4.6 µs for the AD7858 (18t

CLKIN

CLKIN = 4 MHz) and 10 µs for the AD7858L (18t

CLKIN

CLKIN = 1.8 MHz). When a conversion is completed, the

BUSY output goes low, and then the result of the conversion

can be read by accessing the data through the serial interface.

To obtain optimum performance from the part, the read opera-

tion should not occur during the conversion or 400 ns prior to

the next CONVST rising edge. However, the maximum

throughput rates are achieved by reading/writing during conver-

sion, and reading/writing during conversion is likely to degrade

the Signal to (Noise + Distortion) by only 0.5 dBs. The AD7858

can operate at throughput rates up to 200 kHz, 100 kHz for the

AD7858L. For the AD7858 a conversion takes 18 CLKIN

periods; 2 CLKIN periods are needed for the acquisition time

giving a full cycle time of 5 µs (= 200 kHz, CLKIN = 4 MHz).

For the AD7858L 100 kHz throughput can be obtained as

follows: the CLKIN and CONVST signals are arranged to give

a conversion time of 16.5 CLKIN periods as described above,

1.5 CLKIN periods are allowed for the acquisition time. This

gives a full cycle time of 10 µs (=100 kHz, CLKIN = 1.8 MHz).

When using the software conversion start for maximum through-

put the user must ensure the control register write operation

extends beyond the falling edge of BUSY. The falling edge of

BUSY resets the CONVST bit to 0 and allows it to be repro-

grammed to 1 to start the next conversion.

TYPICAL CONNECTION DIAGRAM

Figure 10 shows a typical connection diagram for the AD7858/

AD7858L. The AGND and the DGND pins are connected

together at the device for good noise suppression. The CAL pin

has a 0.01 µF capacitor to enable an automatic self-calibration

on power-up. The conversion result is output in a 16-bit word

with four leading zeros followed by the MSB of the 12-bit result.

Note that after the AV

and DV

power-up the part will

CH1

CH2

CH3

CH4

CH5

OSCILLOSCOPE

4 LEADING

ZEROS FOR

ADC DATA

AUTO CAL ON

POWER-UP

OPTIONAL

EXTERNAL

REFERENCE

AD780/

REF-192

4MHz/1.8MHz OSCILLATOR

MASTER CLOCK

INPUT

0.1␮F

0.1␮F10␮F

ANALOG SUPPLY

+3V TO +5V

0V TO 2.5V

INPUT

0.1␮F

0.01␮F

0.1␮F

INTERNAL/

EXTERNAL

REFERENCE

200kHz/100kHz PULSE GENERATOR

CONVERSION

START INPUT

SERIAL CLOCK

INPUT

FRAME SYNC INPUT

SERIAL DATA INPUT

SERIAL DATA

OUTPUT

DATA GENERATOR

PULSE GENERATOR

CLKIN

SCLK

CONVST

SYNC

DIN

DOUT

DGND

AGND

CAL

SLEEP

REF2

REF1

AIN(–)

AIN(+)

AD7858/

AD7858L

Figure 10. Typical Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

AD7858LARZ

Mfr. #:

Buy AD7858LARZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD7858LARZ

AD7858LARZ

Products related to this Datasheet