AD7858LARZ Datasheet AD7858BRZ, AD7858ARZ, AD7858LARZ | P28-P30

REV. B

–28–

AD7858/AD7858L

MICROPROCESSOR INTERFACING

In many applications, the user may not require the facility of

writing to most of the on-chip registers. The only writing neces-

sary is to set the input channel configuration. After this the

CONVST is applied, a conversion is performed, and the result

may be read using the SCLK to clock out the data from the

output register on to the DOUT pin. At the same time a write

operation occurs and this may consist of all 0s where no data is

written to the part or may set a different input channel configu-

ration for the next conversion. The SCLK may be connected to

the CLKIN pin if the user does not want to have to provide

separate serial and master clocks. With this arrangement the

SYNC signal must be low for 16 SCLK cycles for the read and

write operations.

DIN

DOUT

SYNC

CONVST

CLKIN

SCLK

AD7858/

AD7858L

4MHz/1.8MHz

MASTER CLOCK

SYNC SIGNAL TO

GATE THE SCLK

SERIAL DATA

OUTPUT

CONVERSION START

SERIAL DATA INPUT

Figure 36. Simplified Interface Diagram

AD7858/AD7858L to 8XC51 Interface

Figure 37 shows the AD7858/AD7858L interface to the

8XC51. The 8XL51 is for interfacing to the AD7858/AD7858L

when the supply is at 3 V. The 8XC51 only runs at 5 V. The

8XC51 is in Mode 0 operation. This is a two-wire interface

consisting of the SCLK and the DIN which acts as a bidirec-

tional line. The SYNC is tied low. The BUSY line can be used

to give an interrupt driven system but this would not normally

be the case with the 8XC51. For the 8XC51 12 MHz version

the serial clock will run at a maximum of 1 MHz so the serial

interface of the AD7858/AD7858L will only be running at

1 MHz. The CLKIN signal must be provided separately to the

AD7858/AD7858L from a port line on the 8XC51 or from a

source other than the 8XC51. Here the SCLK cannot be tied to

the CLKIN as the SYNC is tied low permanently. The CONVST

signal can be provided from an external timer or conversion can

be started in software if required. The sequence of events would

typically be to write to the control register via the DIN line setting

a conversion start and the 2-wire interface mode (this would be

performed in two 8-bit writes), wait for the conversion to be

finished (4.6 µs with 4 MHz CLKIN), read the conversion result

data on the DIN line (this would be performed in two 8-bits

reads), and repeat the sequence. The maximum serial frequency

will be determined by the data access and hold times of the

8XC51 and the AD7858/AD7858L.

8XC51/L51

P3.0

P3.1

AD7858/AD7858L

CONVST

CLKIN

SCLK

DIN

SYNC

OPTIONAL

4MHz/1.8MHz

BUSY

(INT0/P3.2)

MASTER

SLAVE

OPTIONAL

Figure 37. 8XC51/PIC16C42 Interface

AD7858/AD7858L to 68HC11/16/L11/PIC16C42 Interface

Figure 38 shows the AD7858/AD7858L SPI/QSPI interface to

the 68HC11/16/L11/PIC16C42. The 68L11 is for interfacing to

the AD7858/AD7858L when the supply is 3 V. The AD7858/

AD7858L is in Interface Mode 2. The SYNC line is not used

and is tied to DGND. The µController is configured as the mas-

ter, by setting the MSTR bit in the SPCR to 1, and provides the

serial clock on the SCK pin. For all the µControllers the CPOL

bit is set to 1 and for the 68HC11/16/L11 the CPHA bit is set to

1. The CLKIN and CONVST signals can be supplied from the

µController or from separate sources. The BUSY signal can be

used as an interrupt to tell the µController when the conversion

is finished, then the reading and writing can take place. If re-

quired the reading and writing can take place during conversion

and there will be no need for the BUSY signal in this case.

68HC11/L11/16

SCK

CONVST

CLKIN

SCLK

DIN

SYNC

OPTIONAL

4MHz/1.8MHz

BUSY

IRQ

MASTER

SLAVE

OPTIONAL

DOUT

MISO

MOSI

SPI

HC16, QSPI

AD7858/AD7858L

Figure 38. 68HC11 and 68HC16 Interface

For the 68HC16 the word length should be set to 16 bits, and

the SS line should be tied to the SYNC pin for the QSPI inter-

face. The micro-sequencer and RAM associated with the

68HC16 QSPI port can be used to perform a number of read

and write operations, and store the conversion results in

memory, independent of the CPU. This is especially useful when

reading the conversion results from all eight channels consecu-

tively. The command section of the QSPI port RAM would be

programmed to perform a conversion on one channel, read the

conversion result, perform a conversion on the next channel,

read the conversion result, and so on until all eight conversion

results are stored into the QSPI RAM.

AD7858/AD7858L

REV. B

–29–

A typical sequence of events would be to write to the control

same time reading data from the previous conversion on the

DOUT line (both the read and write operations would each be

two 8-bit operations, one 16-bit operation for the 68HC16),

wait for the conversion to be finished (= 4.6 µs for AD7858

with 4 MHz CLKIN), and then repeat the sequence. The maxi-

mum serial frequency will be determined by the data access and

hold times of the µControllers and the AD7858/AD7858L.

AD7858/AD7858L to ADSP-21xx Interface

Figure 39 shows the AD7858/AD7858L interface to the ADSP-

21xx. The ADSP-21xx is the master and the AD7858/AD7858L

is the slave. The AD7858/AD7858L is in Interface Mode 2.

For the ADSP-21xx the bits in the serial port control register

should be set up as TFSR = RFSR = 1 (need a frame sync for

every transfer), SLEN = 15 (16-bit word length), TFSW =

RFSW = 1 (alternate framing mode for transmit and receive

operations), INVRFS = INVTFS = 1 (active low RFS and

TFS), IRFS = 0, ITFS = 1 (External RFS and internal TFS),

and ISCLK = 1 (internal serial clock). The CLKIN and

CONVST signals can be supplied from the ADSP-21xx or

from an external source. The serial clock from the ADSP-21xx

must be inverted before the SCLK pin of the AD7858/AD7858L.

This SCLK could also be used to drive the CLKIN input of the

AD7858/AD7858L. The BUSY signal indicates when the con-

version is finished and may not be required. The data access

and hold times of the ADSP-21xx and the AD7858/AD7858L

allow for a serial clock of 4 MHz/1.8 MHz at 5 V and 3.3 MHz/

1.8 MHz at 3 V supplies.

ADSP-21xx

CONVST

CLKIN

DOUT

DIN

SYNC

OPTIONAL

4MHz/1.8MHz

BUSY

IRQ

MASTER

SLAVE

TFS

SCK

SCLK

RFS

OPTIONAL

AD7858/AD7858L

Figure 39. ADSP-21xx Interface

AD7858/AD7858L to DSP56000/1/2/L002 Interface

Figure 40 shows the AD7858/AD7858L to DSP56000/1/2/

L002 interface. Here the DSP5600x is the master and the

AD7858 is the slave. The AD7858/AD7858L is in Interface

Mode 2. The DSP56L002 is used when the AD7858/AD7858L

is being operated at 3 V. The setting of the bits in the registers

of the DSP5600x would be for synchronous operation (SYN =

1), internal frame sync (SCD2 = 1), gated internal clock (GCK

= 1, SCKD = 1), 16-bit word length (WL1 = 1, WL0 = 0). Since

a gated clock is used here the SCLK cannot be tied to the CLKIN

of the AD7858/AD7858L. The SCLK from the DSP5600x

must be inverted before it is applied to the AD7858/AD7858L.

Again the data access and hold times of the DSP5600x and

the AD7858/AD7858L allows for a SCLK of 4 MHz/1.8 MHz.

DSP56000/1/2/L002

SRD

CONVST

CLKIN

SCLK

DIN

SYNC

OPTIONAL

BUSY

IRQ

MASTER

SLAVE

OPTIONAL

DOUT

SC2

STD

SCK

4MHz/1.8MHz

AD7858/AD7858L

Figure 40. DSP56000/1/2 Interface

REV. B

–30–

AD7858/AD7858L

APPLICATION HINTS

Grounding and Layout

The analog and digital supplies to the AD7858/AD7858L are

independent and separately pinned out to minimize coupling

between the analog and digital sections of the device. The part

has very good immunity to noise on the power supplies as can

be seen by the PSRR vs. Frequency graph. However, care

should still be taken with regard to grounding and layout.

The printed circuit board that houses the AD7858/AD7858L

should be designed such that the analog and digital sections are

separated and confined to certain areas of the board. This facili-

tates the use of ground planes that can be separated easily. A

minimum etch technique is generally best for ground planes as

it gives the best shielding. Digital and analog ground planes

should only be joined in one place. If the AD7858/AD7858L is

the only device requiring an AGND to DGND connection,

then the ground planes should be connected at the AGND and

DGND pins of the AD7858/AD7858L. If the AD7858/

AD7858L is in a system where multiple devices require AGND

to DGND connections, the connection should still be made at

one point only, a star ground point which should be established

as close as possible to the AD7858/AD7858L.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD7858/AD7858L to avoid noise coupling.

The power supply lines to the AD7858/AD7858L should use as

large a trace as possible to provide low impedance paths and

reduce the effects of glitches on the power supply line. Fast

switching signals like clocks should be shielded with digital

ground to avoid radiating noise to other sections of the board,

and clock signals should never be run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on oppo-

site sides of the board should run at right angles to each other.

This will reduce the effects of feedthrough through the board. A

microstrip technique is by far the best but is not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to ground planes while signals are

placed on the solder side.

Good decoupling is also important. All analog supplies should

be decoupled with 10 µF tantalum in parallel with 0.1 µF ca-

pacitors to AGND. All digital supplies should have a 0.1 µF

disc ceramic capacitor to AGND. To achieve the best from

these decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. In

systems where a common supply voltage is used to drive both

the AV

and DV

of the AD7858/AD7858L, it is recom-

mended that the system’s AV

supply be used. In this case

there should be a 10 Ω resistor between the AV

pin and

pin. This supply should have the recommended analog

supply decoupling capacitors between the AV

pin of the

AD7858/AD7858L and AGND and the recommended digital

supply decoupling capacitor between the DV

pin of the

AD7858/AD7858L and DGND.

Evaluating the AD7858/AD7858L Performance

The recommended layout for the AD7858/AD7858L is out-

lined in the evaluation board for the AD7858/AD7858L. The

evaluation board package includes a fully assembled and tested

evaluation board, documentation, and software for controlling

the board from the PC via the EVAL-CONTROL BOARD.

The EVAL-CONTROL BOARD can be used in conjunction

with the AD7858/AD7858L Evaluation board, as well as many

other Analog Devices evaluation boards ending in the CB desig-

nator, to demonstrate/evaluate the ac and dc performance of the

AD7858/AD7858L.

The software allows the user to perform ac (fast Fourier trans-

form) and dc (histogram of codes) tests on the AD7858/

AD7858L. It also gives full access to all the AD7858/AD7858L

on-chip registers allowing for various calibration and power-

down options to be programmed.

AD785x Family

All parts are 12 bits, 200 kSPS, 3.0 V to 5.5 V.

AD7853 – Single Channel Serial

AD7854 – Single Channel Parallel

AD7858 – Eight Channel Serial

AD7859 – Eight Channel Parallel

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P32

AD7858LARZ

Mfr. #:

Buy AD7858LARZ

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3-5V SGL Supply 200kSPS 8-Ch 12-Bit

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AD7858LARZ

AD7858LARZ

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