1
LTC3717-1
sn37171 37171fs
Wide Operating Range,
No R
SENSE
TM
Step-Down Controller
for DDR/QDR Memory Termination
■
V
OUT
= 1/2 V
REF
■
Adjustable and Symmetrical Sink/Source
Current Limit up to 20A
■
True Current Mode Control with Optional Use of
Sense Resistor
■
V
ON
and I
ON
Pins Allow Constant Frequency
Operation During Input and Output Voltage Changes
■
±0.65% Output Voltage Accuracy
■
Up to 97% Efficiency
■
Ultrafast Transient Response
■
2% to 90% Duty Cycle at 200kHz
■
t
ON(MIN)
≤ 100ns
■
Stable with Ceramic C
OUT
■
Power Good Output Voltage Monitor
■
Wide V
IN
Range: 4V to 36V
■
Adjustable Switching Frequency up to 1.5MHz
■
Output Overvoltage Protection
■
Optional Short-Circuit Shutdown Timer
■
Available in a 5mm × 5mm QFN Package
■
Bus Termination: DDR and QDR Memory, SSTL,
HSTL, ...
■
Notebook Computers, Desktop Servers
■
Tracking/Margining Power Supply
The LTC
®
3717-1 is a synchronous step-down switching
regulator controller for double data rate (DDR) and Quad
Data Rate
TM
(QDR
TM
) memory termination. The controller
uses a valley current control architecture to deliver very
low duty cycles with or without a sense resistor. Operating
frequency is selected by an external resistor and is com-
pensated for variations in V
IN
and V
OUT
.
Forced continuous operation reduces noise and RF inter-
ference. Output voltage is internally set to half of V
REF
,
which is user programmable.
Fault protection is provided by an output overvoltage
comparator and optional short-circuit shutdown timer.
Soft-start capability for supply sequencing is accom-
plished using an external timing capacitor. The regulator
current limit level is symmetrical and user programmable.
Wide supply range allows operation from 4V to 36V at the
V
CC
input.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No R
SENSE
is a trademark of Linear Technology Corporation.
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress
Semiconductor, Hitachi, IDT, Micron Technology, Inc. and Samsung.
Figure 1. High Efficiency DDR Memory Termination Supply
Efficiency vs Load Current
+
CMDSH-3
B320A
0.68µH
4.7µF
150µF
6.3V
×2
V
IN
2.5V TO 5.5V
V
OUT
1.25V
±10A
+
+
180µF
4V
×2
Si7840DP
37171 F01a
Si7840DP
715k
0.1µF
I
ON
V
REF
TG
SW
DRV
CC
SENSE
+
SENSE
–
BOOST
RUN/SS
I
TH
SGND
INTV
CC
BGV
ON
PGND
V
FB
PGOOD
0.22µF
20k
LTC3717-1
470pF
1µF
V
CC
V
CC
5V TO 28V
B320A
V
DD
= 2.5V
LOAD CURRENT (A)
0
EFFICIENCY (%)
37171 F01b
100
90
80
70
60
50
40
30
20
10
0
2 4 6 8 10 12 14
V
IN
= 2.5V
V
IN
= 5V
V
OUT
= 1.25V
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U