16
LTC3717-1
sn37171 37171fs
APPLICATIO S I FOR ATIO
WUUU
Tying V
RNG
to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 143mV. To check if the current limit is acceptable,
assume a junction temperature of about 40°C above a
70°C ambient with ρ
110°C
= 1.4:
I
mV
AA
LIMIT
+=
143
14 0010
1
2
3 7 12 1
(.)(. )
(. ) .
and double check the assumed T
J
in the MOSFET:
P
VV
V
AW
BOT
=Ω=
25 125
25
12 1 1 4 0 010 1 02
2
.–.
.
(.)(.)(. ) .
T
J
= 70°C + (1.02W)(40°C/W) = 111°C
Because the top MOSFET is on roughly the same amount
of time as the bottom MOSFET, the same Si4874 can be
used as the synchronous MOSFET.
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C
IN
is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013 to minimize output voltage changes due to induc-
tor ripple current and load steps. For current sinking
applications where current flows back to the input through
the top transistor, output capacitors with a similar amount
of bulk C and ESR should be placed on the input as well.
(This is typically the case, since V
IN
is derived from
another DC/DC converter.) The ripple voltage will be only:
V
OUT(RIPPLE)
= I
L(MAX)
(ESR)
= (4A) (0.013) = 52mV
However, a 0A to 10A load step will cause an output
change of up to:
V
OUT(STEP)
= I
LOAD
(ESR) = (10A) (0.013) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.
PC Board Layout Checklist
When laying out a PC board follow one of the two sug-
gested approaches. The simple PC board layout requires
a dedicated ground plane layer. Also, for higher currents,
it is recommended to use a multilayer board to help with
heat sinking power components.
Figure 7. Design Example: 1.25V/±10A at 250kHz
RUN/SS
PGOOD
V
RNG
I
TH
SGND
I
ON
V
FB
V
REF
BOOST
TG
SW
PGND
BG
INTV
CC
V
CC
EXTV
CC
LTC3717-1
SENSE
+
SENSE
V
ON
DRV
CC
+
M2
Si4874
M1
Si4874
L1
0.68µH
D1
B320A
D2
B320A
C
OUT1-2
270µF
2V
×2
C
OUT3
22µF
6.3V
X7R
C
IN
22µF
6.3V
X7R
V
EXT
5V
V
IN
= 2.5V
V
OUT
1.25V
±10A
C
SS
0.1µF
C
C1
470pF
C
ON
0.01µF
C
C2
100pF
C
VCC
4.7µF
C
F
0.1µF
(OPT)
0.1µF
C
B
0.22µF
R
C
20k
R
ON
511k
R
F
1
D
B
CMDSH-3
37171 F07
C
IN
, C
OUT1-2
: CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-0R68MC-H
R
PG
100k
R3
11k
R4
39k
+
+
C
IN
180µF
4V
×2
10
17
LTC3717-1
sn37171 37171fs
APPLICATIO S I FOR ATIO
WUUU
Figure 8. LTC3717-1 Layout Diagram
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
Place C
IN
, C
OUT
, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components on
the bottom side of the board.
Place LTC3717-1 chip with Pins 15 to 28 facing the
power components. Keep the components connected
to Pins 1 to 10 close to LTC3717-1 (noise sensitive
components).
Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3717-1.
Use several bigger vias for power components.
Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
Use planes for V
IN
and V
OUT
to maintain good voltage
filtering and to keep power losses low.
Flood all unused areas on all layers with copper. Flood-
ing with copper will reduce the temperature rise of
power component. You can connect the copper areas to
any DC net (V
IN
, V
OUT
, GND or to any other DC rail in
your system).
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper opera-
tion of the controller. These items are also illustrated in
Figure 8.
Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
Connect the input capacitor(s) C
IN
close to the power
MOSFETs. This capacitor carries the MOSFET AC cur-
rent.
Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
Connect the INTV
CC
and DRV
CC
decoupling capacitor
C
VCC
closely to the INTV
CC
, DRV
CC
and PGND pins.
Connect the top driver boost capacitor C
B
closely to the
BOOST and SW pins.
Connect the V
CC
pin decoupling capacitor C
F
closely to
the V
CC
and PGND pins.
C
C2
BOLD LINES INDICATE HIGH CURRENT PATHS
C
C1
C
SS
C
FB
C
ION
R
ON
R
C
R
F
37171 F08
RUN/SS
PGOOD
V
RNG
I
TH
SGND
I
ON
V
FB
V
REF
BOOST
TG
SW
PGND
BG
INTV
CC
V
CC
EXTV
CC
C
B
M2
M1
D1
D2
D
B
C
F
C
VCC
C
OUT
C
IN
V
IN
V
OUT
+
+
LTC3717-1
L
+
SENSE
+
SENSE
V
ON
DRV
CC
18
LTC3717-1
sn37171 37171fs
TYPICAL APPLICATIO S
U
High Voltage Half (V
IN
) Power Supply
1.5V/±10A at 300kHz from 5V to 28V Input
RUN/SS
PGOOD
V
RNG
I
TH
SGND
I
ON
V
FB
V
REF
BOOST
TG
SW
PGND
BG
INTV
CC
V
CC
EXTV
CC
LTC3717-1
+
M2
IRF7822
M1
IRF7811W
L1
1.2µH
D1
B320A
B320A
C
OUT
270µF
2V
×2
C
IN
10µF
35V
×3
10µF
6.3V
X7R
V
REF
3V
V
IN
5V TO 28V
V
OUT
1.5V
±10A
C
SS
0.1µF
C
C1
680pF
C
ON
0.01µF
C
C2
100pF
C
VCC
4.7µF
C
B
0.22µF
R
C
20k
R
ON
510k
D
B
CMDSH-3
37171 TA01
C
OUT
: CORNELL DUBILIER ESRE271M02B
R
PG
100k
R
R1
11k
R
R2
39k
SENSE
+
SENSE
V
ON
DRV
CC
RUN/SS
PGOOD
V
RNG
I
TH
SGND
I
ON
V
FB
V
REF
BOOST
TG
SW
PGND
BG
INTV
CC
V
CC
EXTV
CC
LTC3717-1
+
M2
FDS6680S
M1
FDS6680S
L1
1.8µH
C
OUT1
270µF
16V
C
OUT2
10µF
15V
C
IN
10µF
25V
×2
V
IN
5V TO 25V
V
OUT
V
IN
/2
±6A
C
SS
0.1µF
C
C1
470pF
C2
2200pF
C
ON
0.01µF
C
C2
100pF
C
VCC
4.7µF
C
F
0.1µF
C
B
0.22µF
R
C
20k
R
ON
510k
R2
1M
D
B
CMDSH-3
37171 TA02
C
IN
: TAIYO YUDEN TMK432BJ106MM
C
OUT1
: SANYO, OS-CON 16SP270
C
OUT2
: TAIYO YUDEN JMK316BJ106ML
L1: TOKO 919AS-1R8N
R
PG
100k
R
F
1
R1 2M
SENSE
+
SENSE
V
ON
DRV
CC

LTC3717EUH-1#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Power Supply for DDR in QFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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