IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
TCR3 – Prescaler Clear
Write only bit. Writing a “1” to this bit resets the prescaler to zero. A read of this location
always indicates a zero. Unaffected by reset.
TCR2, TCR1, TCR0 – Prescaler select bits
Decoded to select one of eight outputs of the prescaler. Unaffected by reset.
TRC2 TRC1 TRC0 RESET
000
1
001
2
010
4
011
8
100
16
101
32
110
64
111
128
Prescaler
Copyright © 2007 IA211081401-03 www.Innovasic.com
Customer Support:
Page 19 of 33 1-888-824-4184
©
IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
Instruction Set Description
The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, read-
modify-write, branch, bit manipulation, and control.
Register/Memory Instructions:
Most of the following instructions use two operands. One is either the accumulator or the
index register and the other is obtained from memory. The jump unconditional (JMP) and
jump to subroutine (JSR) instructions have no register operand.
Function Mnemonic
Load A from memory LDA
Load X from memory LDX
Store A in memory STA
Store X in memory STX
Add memory to A ADD
Add memory and carry to A ADC
Subtract memory SUB
Subtract memory from A with Borrow SBC
AND memory to A AND
OR memory with A ORA
Exclusive OR memory with A EOR
Arithmetic compare A with memory CMP
Arithmetic compare X with memory CPX
Bit test memory with A (logical compare) BIT
Jump Unconditional JMP
Jump to subroutine JSR
Read-Modify-Write Instructions:
These instructions read a memory or register location, modify or test its contents and then
write the modified value back to memory or the register.
Function Mnemonic
Increment INC
Decrement DEC
Clear CLR
Complement COM
Negate (2's complement) NEG
Rotate Left Thru Carry ROL
Rotate Right Thru Carry ROR
Logical shift left LSL
Logical shift right LSR
Arithmetic shift right ASR
Test for negative or zero TST
Copyright © 2007 IA211081401-03 www.Innovasic.com
Customer Support:
Page 20 of 33 1-888-824-4184
©
IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
Bit Manipulation Instructions:
The MPU is capable of altering any bits residing in the first 256 bytes of memory. An
additional feature allows the software to test and branch on the state of any bit within these
locations. For test and branch instructions the value of the bit tested is placed in the carry bit
of the condition code register.
Function
Mnemonic
n = 0…7
Branch if bit n set BRSET n
Branch if bit n clear BRCLR n
Set bit n BSET n
Clear bit n BCLR n
Branch Instructions:
If a specific condition is met, the instruction branches. If not, no operation is performed.
Function Mnemonic
Branch always BRA
Branch never BRN
Branch if higher BHI
Branch if lower or same BLS
Branch if carry clear BCC
Branch if higher or same BHS
Branch if carry set BCS
Branch if lower BLO
Branch if not equal BNE
Branch if equal BEQ
Branch if half carry clear BHCC
Branch if half carry set BHCS
Branch if plus BPL
Branch if minus BMI
Branch if interrupt mask bit clear BMC
Branch if interrupt mask bit set BMS
Branch if interrupt line low BIL
Branch if interrupt line high BIH
Branch to subroutine BSR
Copyright © 2007 IA211081401-03 www.Innovasic.com
Customer Support:
Page 21 of 33 1-888-824-4184
©

IA6805E2PDW40IR0

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Microprocessors - MPU Replacement for Motorola MC146805E2
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet