IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
Functional Description
Memory:
The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations
are divided into internal memory space and external memory space as shown in Figure 5.
The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112
bytes of RAM. The MPU can read from or write to any of these locations. During program
reads from on chip locations, the MPU accepts data only from the addressed on chip
location. Any read data appearing on the input bus is ignored. The shared stack area is used
during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack
usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used
for data storage or temporary work locations, but care must be taken to prevent it from
being overwritten due to stacking from an interrupt or subroutine call.
RAM
(112 BYTES)
I/O PORTS
TIMER RAM
EXTERNAL MEMORY
SPACE (8064 BYTES)
TIMER INTERRUPT FROM WAIT STATE ONLY
TIMER INTERRUPT
EXTERNAL INTERRUPT
SWI
RESET
PORT A DATA REGISTER
PORT B DATA REGISTER
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
TIMER DATA REGISTER
TIMER CONTROL REGISTER
EXTERNAL MEMORY SPACE
$1FF6 - $1FF7
$1FF8 - $1FF9
$1FFA - $1FFB
$1FFC - $1FFD
$1FFE - $1FFF
$0000
$007F
$0080
$00FF
$0100
63
64
127
0
127
128
255
256
8191
INTERRUPT
VECTORS
ACCESS VIA
PAGE 0
DIRECT
ADDRESS
STACK
(64 BYTES MAX)
0
1
2
3
4
5
6
7
8
9
10
15
16
Figure 5. Memory Map
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IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
Registers:
The following paragraphs describe the registers contained in the MPU. Figure 6 shows the
programming model and Figure 7 shows the interrupt stacking order.
A
X
SP10 0 0 0 0 0
H I N Z C
70
CC
CONDITION CODE REGISTER
CARRY/BORROW
HALF CARRY
INTERRUPT MASK
NEGATIVE
ZERO
STACK POINTER
PROGRAM COUNTER
INDEX REGISTER
ACCUMULATOR
70
12 078
PCH
PCL
12 6 0
4
0
Fi
g
ure 6. Pro
g
rammin
g
Model
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
CONDITION CODE
REGISTER
ACCUMULATOR
INDEX REGISTER
111
I
N
T
E
R
R
U
P
T
DECREASING MEMORY
ADDRESSES
STACK
PCH000
PCL
R
E
T
U
R
N
INCREASING MEMORY
ADDRESSES
UNSTACK
Figure 7. Interrupt Stacking Order
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©
IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
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©
A(Accumulator):
The accumulator is an 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
X(Index Register):
The index register is an 8-bit register used during the indexed addressing mode. It contains
an 8-bit value used to create an effective address. The index register may also be used as a
temporary storage area when not performing addressing operations.
PC(Program Counter):
The program counter is a 13-bit register that holds the address of the next instruction to be
performed by the MPU.
SP(Stack Pointer):
The stack pointer is a 13-bit register that holds the address of the next free location on the
stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is
set to location $007f. The seven most significant bits of the stack pointer are permanently
set to 0000001. They are appended to the six least significant register bits to produce an
address range down to location $0040. The stack pointer gets decremented as data is pushed
onto the stack and incremented as data is removed from the stack. The stack area of RAM is
used to store the return address on subroutine calls and the machine state during interrupts.
The maximum number of locations for the stack pointer is 64 bytes. If the stack goes
beyond this limit the stack pointer wraps around and points to its upper limit thereby losing
the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and
interrupts use 5 bytes.
CC(Condition code Register):
The condition code register is a 5-bit register that indicates the results of the instruction just
executed. The bit is set if it is high. A program can individually test these bits and specific
actions can be taken as a result of their states. Following is an explanation of each bit.
C(Carry Bit):
The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU)
occurred during the last arithmetic instruction. This bit is also modified during bit test, shift,
rotate, and branch types of instructions.
Z(Zero Bit):
The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero.
N(Negative Bit):
The negative bit indicates the result to the last arithmetic, logical, or data manipulation was
negative (bit 7 in the result is high).

IA6805E2PDW40IR0

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Microprocessors - MPU Replacement for Motorola MC146805E2
Lifecycle:
New from this manufacturer.
Delivery:
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