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IA6805E2PDW40IR0

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33
IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
Control Instructions:
These are used to control processor operation during program execution. They are register
reference instructions.
Function Mnemonic
Transfer A to X TAX
Transfer X to A TXA
Set carry bit SEC
Clear carry bit CLC
Set interrupt mask bit SEI
Clear interrupt mask bit CLI
Software interrupt SWI
Return from subroutine RTS
Return from interrupt RTI
Reset stack pointer RSP
No-Operation NOP
Stop STOP
Wait WAIT
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Customer Support:
Page 22 of 33 1-888-824-4184
©
IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
Opcode Map Summary:
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Hi Hi
Low Low
5 5 3533659 234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 6 234543
3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
553 234543
3BTB2 BSC2REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 35336510 234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
553 234543
3BTB2 BSC2REL 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 2 45654
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 2234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 2234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 2234543
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
553 2234543
3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 353365 2 23432
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 343364 2656765
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 3 2 234543
3 BTB 2 BSC 2 REL 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
5 5 35336522 45654
3 BTB 2 BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH 1 INH 2 DIR 3 EXT 3 IX2 2 IX1 1 IX
IX1IX2 IX
Branch Read-Modify-Write Control Register/Memory
INH IMM DIR EXT
F 1111
BTB BSC REL DIR INH INH IX1 IX INH
ROR
LSR
8
1000
7
0111
CMP CMP
AND
LDA
CMP
SBC
CPX
AND
CMP CMP CMP
SBC SBC SBC SBC
E
1110
F
1111
C
1100
D
11011010
AB
1011
9
1001
Bit Manipulation
RTS
5
0101
6
0110
0
0000
BRSET0 NEGA
2
0010
3
0011
4
0100
0
0000
BSET0 BRA NEG NEGX NEG NEG RTI SUB SUB SUB SUB SUB SUB
BRCLR0 BCLR0 BRN
0 0000
1 0001
2 0010
BRSET1 BSET1 BHI SBC
SWI
3 0011
CPX CPX CPX CPX
4 0100
5 0101
COMA COMX COM COM CPX
BIT BIT
EO
R
BRCLR1 BCLR1 BLS COM
BIT
LDA
LSRA AND AND ANDANDLSRBRSET2 BSET2 BCC LSR LSRX
BITBRCLR2 BCLR2 BCS
A 1010
9 1001
7 0111
6 0110
8 1000
BIT BIT
EO
R
EO
R
RORA RORX ROR LDABRSET3 BSET3 BNE ROR
D 1101
LDA LDA LDA
STA STA STA
EOR
C 1100
B 1011
E 1110
BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR
T
AX STA STA
BRSET4 BSET4 BHCC LSL LSLA LSLX LSL LSL CLC EOR EO
R
BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL SEC ADC ADC ADC ADC ADC ADC
BRSET5 BSET5 BPL DEC DECA DECX DEC DEC CLI ORA ORA ORA ORA ORA ORA
BRCLR5 BCLR5 BMI SEI ADD ADD ADD ADD ADD ADD
BRSET6 BSET6 BMC INC INCA INCX INC INC RSP
J
MP
J
MP
J
MP
J
MP
J
MP
BRCLR6 BCLR6 BMS
T
ST
T
STA
T
STX
T
ST
T
ST NOP BSR
J
SR
J
SR
J
SR
J
SR
J
SR
BRSET7 BSET7 BIL STOP LDX LDX LDX LDX LDX LDX
BRCLR7 BCLR7 BIH CL
R
CLRA CLRX CL
R
CLR WAIT
T
XA STX STX STX STX STX
6
0110
7
0111
8
1000
1
0001
2
0010
3
0011
4
0100
D
1101
E
1110
F
1111
1
0001
9
1001
A
1010
B
1011
C
1100
5
0101
Abbreviations for Address
Modes:
Copyright © 2007 IA211081401-03 www.Innovasic.com
Customer Support:
INH Inherent
A Accumulator
X Index Register
IMM Immediate
DIR Direct
EXT Extended
REL Relative
BSC Bit set/clear
SUB
3
IX
1
F
1111
0
0000
Opcode in Hexadecimal
Opcode in Binary
Address Mode
Mnemonic
Bytes
# of Cycles
BTB Bit test and branch
IX Indexed, no offset
IX1 Indexed, 1 byte offset
IX2 Indexed, 2 byte offset
Legend:
Page 23 of 33 1-888-824-4184
©
IA6805E2 29 August 2007
Microprocessor Unit
As of Production Version 00
AC/DC Parameters
Absolute maximum ratings:
Supply Voltage (V
DD
)........................….…...………….….………-0.3V to 6V
Input Pin Voltage (V
IN
)…………………………………...-0.3 to V
DD
+0.3V
Operating Temperature……………………………….……....-40°C to 85°C
Storage temperature Range (Tstg).................…........….…...…- 55°C to 150°C
ESD Protection (HBM)………………………………………………5000V
Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed
under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability
of the device.
DC Characteristics
(V
DD
=4.5 to 5.5 Vdc, V
SS
=0, T
A
=T
L
to T
H
), unless otherwise specified
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Customer Support:
Page 24 of 33 1-888-824-4184
©
A
A
Symbol Parameter Min Max Unit
V
DD
Supply Voltage 4.5 5.5 V
V
OL
-0.4V
V
OH
3.5 - V
I
OL
-2m
I
OH
--2m
V
IH
High Level input Voltage 2 - V
V
IL
Low Level input Voltage - 0.8 V
I
IH
High Level input Current - 1 µA
I
IL
Low Level input Current - -1 µA
Vt- Schmitt Negative Threshold 1.1 - V
Vt+ Schmitt Positive Threshold - 1.87 V
Frequency of Operation
f
OSC
Crystal - 5 MHz
f
OSC
External Clock DC 5 MHz
DC CHARACTERISTICS
Output Current
Output Voltage, I
LOAD
≤ 2
mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33

IA6805E2PDW40IR0

Mfr. #:
Buy IA6805E2PDW40IR0
Manufacturer:
Analog Devices Inc.
Description:
Microprocessors - MPU Replacement for Motorola MC146805E2
Lifecycle:
New from this manufacturer.
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