TLE 7209-2R
Electrical Characteristics
Final Datasheet 25 V1.3, 2005-jan-11
SPI Timing (see Figure 13)
3.4.54 Cycle-Time (1)
t
cyc
(1) 200 – – ns referred to master
3.4.55 Enable Lead Time
t
lead
(2) 100 – – ns referred to master
3.4.56 Enable Lag Time
t
lag
(3) 150 – – ns referred to master
3.4.57 Data Valid
t
v
(4) –
–
–
–
40
150
ns
ns
C
L
= 40 pF
C
L
= 200 pF
referred to TLE 7209-
2R
3.4.58 Data Setup Time
t
su
(5) 50 – – ns referred to master
3.4.59 Data Hold Time
t
h
(6) 20 – – ns referred to master
3.4.60 Disable Time
t
dis
(7) – – 100 ns referred to TLE 7209-
2R; specified by
design
3.4.61 Transfer Delay
t
dt
(8) 150 – – ns referred to master
3.4.62 Select time
t
CSN
(9) 50 – – ns referred to master
3.4.63 Access time
t
acc
(10) 8.35 – – µs referred to master
3.4.64 Clock inactive before
chip select becomes
valid
(11) 200 – – ns –
3.4.65 Clock inactive after
chip select becomes
invalid
(12) 200 – – ns –
Temperature Thresholds
3.4.66 Start of current limit
reduction
T
ILR
150 165 – °C
3.4.67 Thermal Shut-down
T
SD
175 – – °C
Note: Temperature thresholds are not subject to production test; specified by design
3.4 Electrical Characteristics (cont’d)
5V < V
S
< 28V; – 40 °C < T
j
< 150 °C; unless otherwise specified
Pos. Parameter Symbol Limit Values Unit Test Conditions
min. typ. max.
