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DEMOBOARD TLE 7209-2R

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
TLE 7209-2R
Circuit Description
Final Datasheet 7 V1.3, 2005-jan-11
2.2.2 Temperature-depending Current Reduction
For T
ILR
< T
j
<T
SD
the current limit decreases from I
L
=6.6A± 1.1 A to
I
L
=2.5A± 1.1 A as shown in Figure 4
Figure 4 Temperature dependent current reduction
2.3 Protection
The TLE 7209-2R is protected against short circuits, overload and invalid supply voltage
by the following measures:
2.3.1 Short circuit to Ground
The high-side switches are protected against a short of the output to ground by an over
current shut-down. If a high-side switch is turned on and the current rises above the short
circuit detection current
I
OUK
all output transistors are turned off after a typical filter time
of 2 µs, and the error bit “Short Circuit to Ground on output 1 (2)”, SCG1 (SCG2) is stored
in the internal status register.
2.3.2 Short circuit to V
S
Due to the chopper current regulation, the low-side switches are already protected
against a short to the supply voltage. To be able to distinguish a short circuit from normal
current limit operation, the current limitation is deactivated for the blanking time
t
b
after
the current has exceeded the current limit threshold
I
L
. If the short circuit detection
current
I
OUK
is reached within this blanking time, a short circuit is detected (see
Figure 5). All output transistors are turned OFF and the according error bit “Short Circuit
to Battery on output 1 (2)”, SCB1 (SCB2) is set.
A
6.6A
2.5A
Tj
°C
T
SD
tol er ance of temper atur e
dependent cur rent
reduction
range of over -
temper ature shut- down
I
L
T
ILR
TLE 7209-2R
Circuit Description
Final Datasheet 8 V1.3, 2005-jan-11
Figure 5 Short to Vs detection. Left: normal operation. Right: short circuit is
detected
2.3.3 Short circuit across the load
If short circuit messages from high- and low-side switch occur simultaneously within a
delay time of typically 2µs, the error bit “Short Circuit Over Load”, SCOL is set.
2.3.4 Over-Temperature
In case of high DC-currents, insufficient cooling or high ambient temperature, the chip
temperature may rise above the thermal shut-down temperature
T
SD
. In that case, all
output transistors are shut-down and the error-bit “Over-Temperature”, OT is set.
2.3.5 Under-Voltage shut-down
If the supply-voltage at the V
S
pins falls below the under-voltage detection threshold, the
outputs are set to tristate and the error-bit “Under-Voltage at
V
S
“ is set.
2.4 Diagnosis
The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag
Diagnosis. The choice of the Diagnosis-Mode is selected by the voltage-level on Pin 12
(DMS Diagnosis Mode Selection):
• DMS = GND, Status-Flag Mode
•DMS =
V
CC
, SPI-Diagnosis Mode
For the connection of Pins SDI, SDO, CSN and SCK/SF see Figure 14 and Figure 15.
I
OUT
I
L
time
t
b
I
OUK
IN
I
OUT
I
L
time
t
b
I
OUK
IN
t
a
t
b
TLE 7209-2R
Circuit Description
Final Datasheet 9 V1.3, 2005-jan-11
2.4.1 Status-Flag (SF) Mode (DMS = GND)
2.4.1.1 SF output
In SF-mode, pin 2 is used as an open-drain output status-flag. The pin has to be pulled
to the logic supply voltage with a pull-up resistor, 47 kOhm recommended.
In case of any failure that leads to a shut-down of the outputs, the status-flag is set (e.g.
SF pin pulled to low). These failures are:
– Under Voltage on
V
S
– Short circuit of OUT1 or OUT2 against V
S
or GND
– Short circuit between OUT1 and OUT2
– Over-current
– Over-temperature
SF is also pulled low when the outputs are disabled by EN or DIS.
2.4.1.2 Fault storage and reset
– In case of under-Voltage, the failure is not latched. As soon as
V
S
falls below the
under-Voltage detection threshold, the output stage switches in tristate and the status-
flag is set from high level to low-level. If the voltage has risen above the specified value
again, the output stage switches on again and the status-flag is reset to high-level.
The Under Voltage failure is shown at the SF pin for
V
S
in the voltage range below the
detection threshold (typical 4.2V) down to 2.5V.
– In the SF-mode, all internal circuitry is supplied by the voltage on
V
S
. For that reason,
a loss of
V
S
supply voltage leads to a reset of all stored information (Power-ON-
Reset). This Power-ON-Reset occurs as soon as under-Voltage is detected on
V
S
– In case of short circuit, over-current or over-temperature, the fault will be stored.
The output stage remains in tristate and the status-flag at low-level until the error is
reset by one of the following conditions: H -> L on DIS, L -> H on EN or Power-ON
Reset.
2.4.2 SPI-Mode (DMS = 5V)
2.4.2.1 SPI-Interface
The serial SPI interface establishes a communication link between TLE 7209-2R and the
systems microcontroller. The TLE 7209-2R always operates in slave mode whereas the
controller provides the master function. The maximum baud rate is 2 MBaud (200pF on
SDO).
By applying an active slave select signal at CSN the TLE 7209-2R is selected by the SPI
master. SDI is the data input (Slave In), SDO the data output (Slave Out). Via SCK
(Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave
select signal (High) the data output SDO goes into tristate.
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DEMOBOARD TLE 7209-2R

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Manufacturer:
Infineon Technologies
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BOARD DEMO FOR TLE 7209-2R
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