AD7892
REV. C
–9–
CIRCUIT DESCRIPTION
The AD7892 is a fast, 12-bit single supply A/D converter. It
provides the user with signal scaling, track/hold, reference, A/D
converter and versatile interface logic functions on a single chip.
The signal scaling on the AD7892-1 allows the part to handle
either ± 5 V or ± 10 V input signals while operating from a single
+5 V supply. The AD7892-2 handles a 0 V to +2.5 V analog
input range, while signal scaling on the AD7892-3 allows it to
handle ± 2.5 V input signals when operating from a single supply.
The part requires a +2.5 V reference which can be provided from
the part’s own internal reference or from an external reference
source.
Conversion is initiated on the AD7892 by pulsing the CONVST
input. On the rising edge of CONVST, the track/hold goes
from track mode to hold mode and the conversion sequence is
started. At the end of conversion (falling edge of EOC), the
track/hold returns to tracking mode and the acquisition time
begins. Conversion time for the part is 1.47 µs (AD7892-3) and
the track/hold acquisition time is 200 ns (AD7892-3). This allows
the AD7892-3 to operate at throughput rates up to 600 kSPS.
The AD7892-1 and AD7892-2 are specified with a 1.6 µs con-
version and 400 ns acquisition time allowing a throughput rate
of 500 kSPS.
Track/Hold Section
The track/hold amplifier on the AD7892 allows the ADC to
accurately convert an input sine wave of full-scale amplitude to
12-bit accuracy. The input bandwidth of the track/hold is greater
than the Nyquist rate of the ADC even when the ADC is oper-
ated at its maximum throughput rate of 600 kHz (i.e., the track/
hold can handle input frequencies in excess of 300 kHz).
The track/hold amplifier acquires an input signal to 12-bit accu-
racy in less than 200 ns. The operation of the track/hold is
essentially transparent to the user. The track/hold amplifier
goes from its tracking mode to its hold mode on the rising edge
of CONVST. The aperture time for the track/hold (i.e., the
delay time between the external CONVST signal and the track/
hold actually going into hold) is typically 15 ns. At the end of
conversion, the part returns to its tracking mode. The acquisi-
tion time of the track/hold amplifier begins at this point.
Reference Section
The AD7892 contains a single reference pin, labelled REF OUT/
REF IN, which either provides access to the part’s own +2.5 V
reference or to which an external +2.5 V reference can be con-
nected to provide the reference source for the part. The part is
specified with a +2.5 V reference voltage. Errors in the refer-
ence source will result in gain errors in the AD7892’s transfer
function and will add to the specified full-scale errors on the
part. On the AD7892-1 and AD7892-3, it will also result in an
offset error injected in the attenuator stage.
The AD7892 contains an on-chip +2.5 V reference. To use this
reference as the reference source for the AD7892, simply con-
nect a 0.1 µF disc ceramic capacitor from the REF OUT/
REF IN pin to AGND. The voltage that appears at this pin is
internally buffered before being applied to the ADC. If this
reference is required for use external to the AD7892, it should
be buffered as the part has a FET switch in series with the refer-
ence output resulting in a source impedance for this output of
5.5 kΩ nominal. The tolerance on the internal reference is
± 10 mV at 25°C with a typical temperature coefficient of
25 ppm/°C and a maximum error over temperature of ± 25 mV.
If the application requires a reference with a tighter tolerance or
the AD7892 needs to be used with a system reference, then the
user has the option of connecting an external reference to this
REF OUT/REF IN pin. The external reference will effectively
overdrive the internal reference and thus provide the reference
source for the ADC. The reference input is buffered before
being applied to the ADC with the maximum input current is
± 100 µA. Suitable reference sources for the AD7892 include the
AD680, AD780 and REF43 precision +2.5 V references.
INTERFACING
The part provides two interface options, a 12-bit parallel inter-
face and a three-wire serial interface. The required interface
mode is selected via the MODE pin. The two interface modes
are discussed in the following sections.
Parallel Interface Mode
The parallel interface mode is selected by tying the MODE
input to a logic high. Figure 2 shows a timing diagram illustrat-
ing the operational sequence of the AD7892. The on-chip
track/hold goes into hold mode, and conversion is initiated on
the rising edge of the CONVST signal. When conversion is
complete, the end of conversion line (EOC) pulses low to indi-
cate that new data is available in the AD7892’s output register.
This EOC line can be used to drive an edge-triggered interrupt
of a microprocessor. The falling edge of the RD signal should
occur 200 ns prior to the next rising edge of CONVST. CS and
RD going low accesses the 12-bit conversion result. In systems
where the part is interfaced to a gate array or ASIC, this EOC
VALID
DATA
t
CONV
t
8
t
5
t
4
t
7
t
6
t
2
t
1
THREE-STATE
CONVST (I)
EOC (O)
CS (I)
RD (I)
DB0–DB11 (O)
NOTE:
I = INPUT; O = OUTPUT
t
ACQ
t
3
t
9
THREE-STATE
Figure 2. Parallel Mode Timing Diagram
