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AD7892ANZ-1

P1-P3P4-P6P7-P9P10-P12P13-P15
ABSOLUTE MAXIMUM RATINGS*
(T
A
= +25°C unless otherwise noted)
V
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
AD7892-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 17 V
AD7892-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
AD7892-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 7 V
Reference Input Voltage to AGND . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Parameter A Versions
1
B Versions S Version
2
Unit Test Conditions/Comments
LOGIC OUTPUTS
Output High Voltage, V
OH
4.0 4.0 4.0 V min I
SOURCE
= 200 µA
Output Low Voltage, V
OL
0.4 0.4 0.4 V max I
SINK
= 1.6 mA
DB11–DB0
Floating-State Leakage Current ± 10 ± 10 ± 10 µA max
Floating-State Capacitance
4
15 15 15 pF max
Output Coding
AD7892-1 and AD7892-3 Two’s Complement
AD7892-2 Straight (Natural) Binary
CONVERSION RATE
Conversion Time 1.47 1.47 µs max AD7892-3
Track/Hold Acquisition Time
3
0.2 0.2 µs max AD7892-3
Conversion Time 1.6 1.6 1.68 µs max AD7892-1 and AD7892-2
Track/Hold Acquisition Time
3
0.4 0.4 0.32 µs max AD7892-1 and AD7892-2
POWER REQUIREMENTS
V
DD
+5 +5 +5 V nom ± 5% for Specified Performance
I
DD
5
Normal Operation 18 18 19 mA max
Standby Mode
6
AD7892-2 250 250 µA typ
AD7892-3, AD7892-1 80 80 100 µA max typ 15 µA
Power Dissipation
5
Normal Operation 90 90 95 mW max V
DD
= +5 V. Typically 60 mW
Standby Mode
6
AD7892-2 1.25 1.25 mW typ
AD7892-3, AD7892-1 400 400 500 µW max V
DD
= +5 V. Typically 75 µW
NOTES
1
Temperature ranges are as follows: A, B Versions: –40°C to +85°C; S Version: –55°C to +125°C.
2
S Version available on AD7892-1 and AD7892-2 only.
3
See Terminology.
4
Sample tested @ +25°C to ensure compliance.
5
These normal mode and standby mode currents are achieved with resistors (in the range 10 kΩ to 100 kΩ) to either DGND or V
DD
on Pins 8, 9, 16 and 17.
6
A conversion should not be initiated on the part within 30 µs of exiting standby mode.
Specifications subject to change without notice.
AD7892
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +260°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
REV. C
–3–
AD7892
–4–
REV. C
TIMING CHARACTERISTICS
1, 2
A, B S
Parameter Versions Version Unit Test Conditions/Comments
t
CONV
1.47 µs max Conversion Time for AD7892-3
1.6 1.68 µs max Conversion Time for AD7892-1, AD7892-2
t
ACQ
200 ns min Acquisition Time for AD7892-3
400 320 ns min Acquisition Time for AD7892-1, AD7892-2
Parallel Interface
t
1
35 45 ns min CONVST Pulsewidth
t
2
60 60 ns min EOC Pulsewidth
t
3
0 0 ns min EOC Falling Edge to CS Falling Edge Setup Time
t
4
0 0 ns min CS to RD Setup Time
t
5
35 45 ns min Read Pulsewidth
t
6
3
35 40 ns max Data Access Time After Falling Edge of RD
t
7
4
5 5 ns min Bus Relinquish Time After Rising Edge of RD
30 40 ns max
t
8
0 0 ns min CS to RD Hold Time
t
9
200 200 ns min RD to CONVST Setup Time
Serial Interface
t
10
30 35 ns min RFS Low to SCLK Falling Edge Setup Time
t
11
3
25 30 ns max RFS Low to Data Valid Delay
t
12
25 25 ns min SCLK High Pulsewidth
t
13
25 25 ns min SCLK Low Pulsewidth
t
14
3
5 5 ns min SCLK Rising Edge to Data Valid Hold Time
t
15
3
25 30 ns max SCLK Rising Edge to Data Valid Delay
t
16
20 30 ns min RFS to SCLK Falling Edge Hold Time
t
17
4
0 0 ns min Bus Relinquish Time after Rising Edge of RFS
30 30 ns max
t
17A
4
0 0 ns min Bus Relinquish Time after Rising Edge of SCLK
30 30 ns max
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V.
2
See Figures 2 and 3.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
5
Assumes CMOS loads on the data bits. With TTL loads, more current is drawn from the data lines and the RD to CONVST time needs to be extended to 400 ns min.
Specifications subject to change without notice.
1.6mA
+1.6V
200␮A
50pF
TO
OUTPUT
PIN
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7892 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
(V
DD
= +5 V ⴞ 5%, AGND = DGND = 0 V, REF IN = +2.5 V)
WARNING!
ESD SENSITIVE DEVICE
AD7892
REV. C
–5–
ORDERING GUIDE
Input Sample Relative Temperature Package
Model Range Rate Accuracy Range Option
1
AD7892AN-1 ± 5 V or ± 10 V 500 kSPS –40°C to +85°C N-24
AD7892BN-1 ± 5 V or ± 10 V 500 kSPS ± 1 LSB –40°C to +85°C N-24
AD7892AR-1 ± 5 V or ± 10 V 500 kSPS –40°C to +85°C R-24
AD7892BR-1 ± 5 V or ± 10 V 500 kSPS ± 1 LSB –40°C to +85°C R-24
AD7892SQ-1 ± 5 V or ± 10 V 500 kSPS ± 1 LSB –55°C to +125°CQ-24
AD7892AN-2 0 V to +2.5 V 500 kSPS –40°C to +85°C N-24
AD7892BN-2 0 V to +2.5 V 500 kSPS ± 1 LSB –40°C to +85°C N-24
AD7892AR-2 0 V to +2.5 V 500 kSPS –40°C to +85°C R-24
AD7892BR-2 0 V to +2.5 V 500 kSPS ± 1 LSB –40°C to +85°C R-24
AD7892AN-3 ± 2.5 V 600 kSPS –40°C to +85°C N-24
AD7892BN-3 ± 2.5 V 600 kSPS ± 1 LSB –40°C to +85°C N-24
AD7892AR-3 ± 2.5 V 600 kSPS –40°C to +85°C R-24
AD7892BR-3 ± 2.5 V 600 kSPS ± 1 LSB –40°C to +85°C R-24
EVAL-AD7892-2CB
2
Evaluation Board
EVAL-AD7892-3CB
2
Evaluation Board
EVAL-CONTROL BOARD
3
Controller Board
NOTES
1
N = Plastic DIP; Q = Cerdip; R = SOIC.
2
These boards can be used as stand-alone evaluation boards or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration purposes.
3
This board is a complete unit allowing a PC to control and communicate with all Analog Devices’ evaluation boards ending in the CB designators.
P1-P3P4-P6P7-P9P10-P12P13-P15

AD7892ANZ-1

Mfr. #:
Buy AD7892ANZ-1
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Bipolar Input Parallel 12B 600kSPS
Lifecycle:
New from this manufacturer.
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