AD7892
–12–
REV. C
MICROPROCESSOR INTERFACING
The AD7892 features both high speed parallel and serial inter-
faces, allowing considerable flexibility in interfacing to micro-
processor systems. To obtain optimum performance from the
part, data should not be read during conversion and this limits
the achievable throughput rate in serial mode to 400 kSPS for
the AD7892-3.
Figures 6, 7 and 9 show some typical interface circuits between
the AD7892 and popular DSP processors. Figure 8 shows an
interface between the part and a gate array or ASIC where data
is clocked into the ASIC by the AD7892 itself at the end of
conversion. In all cases, the CONVST signal is generated from
an external timer to ensure equidistant sampling.
AD7892 to ADSP-2101 Interface
Figure 6 shows a parallel interface between the AD7892 and the
ADSP-2101 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output pro-
vides an interrupt request to the ADSP-2101.
ADSP-2101
AD7892
ADDRESS DECODE
LOGIC
CONVST
CS
RD
DB11DB0
DATA BUS
ADDRESS BUS
DMA13DMA0
DMD15DMD0
IRQn
DMS
RD
EOC
EN
TIMER
Figure 6. AD7892 to ADSP-2101
AD7892 to TMS320C25 Interface
Figure 7 shows a parallel interface between the AD7892 and the
TMS320C25 DSP processor. CONVST starts conversion and
at the end of conversion the falling edge of the EOC output
provides an interrupt request to the TMS320C25.
TMS320C25
AD7892
ADDRESS DECODE
LOGIC
CONVST
CS
RD
DATA BUS
ADDRESS BUSA15A0
D15D0
STRB
IS
INT
EOC
EN
TIMER
G2
READY
MSC
R/W
DB11DB0
Figure 7. AD7892 to TMS320C25 Interface
EOC Pulse Provides CS and RD
Figure 8 shows a parallel interface between the AD7892 and a
gate array or ASIC. CONVST starts conversion and at the end
of conversion the falling edge of the EOC output provides the
CS and RD pulse to latch data out of the AD7892 and into the
gate array/ASIC. This scheme allows for the fastest possible
throughput rate with the part as no time is lost in interrupt
service routines and as soon as data is available from the part it
is transferred out of it.
GATE
ARRAY/ASIC
AD7892
CONVST
CS
RD
DB11DB0
DATA BUS
DB11DB0
ENABLE
EOC
TIMER
Figure 8. AD7892 to Gate Array/ASIC Interface
AD7892 to DSP56000 Interface
Figure 9 shows a serial interface between the AD7892 and the
DSP56000 DSP processor. CONVST starts conversion and at
the end of conversion the falling edge of the EOC output pro-
vides an interrupt request to the DSP56000.
AD7892
CONVST
RFS
SDATA
EOC
TIMER
SCLK
DSP56000
SC1
SRD
IRQA
SCK
Figure 9. AD7892 to DSP56000 Interface
AD7892
REV. C
–13–
Grounding and Layout
The AD7892 has a single supply voltage pin, V
DD
, which sup-
plies both the analog and digital circuitry on the part. For opti-
mum performance from the part, it is recommended that this
+5 V is taken from the +5 V analog supply in the system. The
analog and digital grounds to the AD7892 are independent and
separately pinned out to minimize coupling between the analog
and digital sections of the device. The part exhibits good immu-
nity to noise on the supplies but care must still be taken with
regard to grounding and layout especially when using switching
mode supplies.
The printed circuit board which houses the AD7892 should be
designed such that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes which can be separated easily. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should only be
joined in one place. If the AD7892 is the only device requiring
an AGND to DGND connection, then the ground planes
should be connected at the AGND and DGND pins of the
AD7892. If the AD7892 is in a system where multiple devices
require AGND to DGND connections, the connection should
still be made at one point only, a star ground point which
should be established as close as possible to the AD7892.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7892 to avoid noise coupling. The power
supply lines to the AD7892 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals like
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is important when using high resolution ADCs.
All analog supplies should be decoupled with 10 µF tantalum in
parallel with 0.1 µF capacitors to AGND. To achieve the best
from these decoupling components, they have to be placed as
close as possible to the device, ideally right up against the device.
All logic chips should be decoupled with 0.1 µF disc ceramic
capacitors to DGND. It is recommended that the system’s
AV
DD
supply is used to supply the V
DD
for the AD7892. This
supply should have the recommended analog supply decoupling
capacitors between the V
DD
pin of the AD7892 and AGND and
the recommended digital supply decoupling capacitor between
the V
DD
pin of the AD7892 and DGND.
Evaluating the AD7892 Performance
The recommended layout for the AD7892 is outlined in the
evaluation board for the AD7892. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation and software for controlling the board from a PC
using the EVAL-CONTROL BOARD. The EVAL-CONTROL
BOARD can be used in conjunction with the AD7892 evalua-
tion board, as well as many other Analog Devices evaluation
boards ending in the CB designator. Using the EVAL-CONTROL
BOARD with the AD7892 evaluation board allows the user to
evaluate the ac and dc performance of the AD7892 on a PC.
The software provided with the evaluation board allows the user
to perform ac (Fast Fourier Transform) and dc (histogram of
codes) tests on the AD7892. The evaluation board can also
be used in a stand-alone fashion without the EVAL-CONTROL
BOARD but in this case, the user has to write their own software
to evaluate the part. There are two versions of the evaluation
board available, one for the AD7892-2 and one for the AD7892-3.
To order the AD7892-2 evaluation board, the order number is
EVAL-AD7892-2CB and to order the AD7892-3 evaluation
board, the order number is EVAL-AD7892-3CB.
AD7892
–14–
REV. C
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-24)
24
112
13
0.260 ± 0.001
(6.61 ± 0.03)
PIN 1
1.228 (31.19)
1.226 (31.14)
0.11 (2.79)
0.09 (2.28)
SEATING
PLANE
0.02 (0.5)
0.016 (0.41)
0.130 (3.30)
0.128 (3.25)
0.07 (1.78)
0.05 (1.27)
0.32 (8.128)
0.30 (7.62)
0.011 (0.28)
0.009 (0.23)
15
0
Cerdip (Q-24)
24
1
12
13
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13) MIN
0.098 (2.49) MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.200 (5.08)
MAX
1.280 (32.51) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.070 (1.78)
0.030 (0.76)
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SOIC (R-24)
24
13
121
0.614 (15.6)
0.598 (15.2)
0.419 (10.65)
0.394 (10.00)
0.299 (7.60)
0.291(7.40)
PIN 1
SEATING
PLANE
0.012 (0.30)
0.004 (0.10)
0.019 (0.49)
0.014 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.050
(1.27)
BSC
0.013 (0.32)
0.009 (0.23)
0.050 (1.27)
0.015 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
45
C1933c–2.5–6/00 (rev. C) 01359
PRINTED IN U.S.A.

AD7892ANZ-1

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Bipolar Input Parallel 12B 600kSPS
Lifecycle:
New from this manufacturer.
Delivery:
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