XRD9827
16
Rev. 3.00
CIS Mode Timing -- DC Coupled
(CLAMP disabled)
ADCCLK
tckhw
tcklw
tckpd
tap
tap
Pixel N-1 Pixel N
tdv
Pixel N+1
CIS
tdv
[5:0]
[11:6]
N-8
MSB
N-8
LSB
N-7
MSB
N-7
LSB
N-6
MSB
N-6
LSB
N-5
MSB
N-5
LSB
DB
Figure 6. Timing Diagram for Figure 5
ADCCLK Events
ADC Sample & PGA Start Tracking next Pixel
MSB Data Out
LSB Data Out
HI ADC Track PGA Output
LO ADC Hold/Convert
Table 1.
Mode 2. AC Coupled
If the CIS signal has a black reference for the video
signal, an external capacitor C
EXT
is used. When
CLAMP (clamp) pin is set high an internal switch allows
one side of the external capacitor to be set to ground.
It then is level shifted to correspond to the bottom ladder
reference voltage of the ADC (Figure 7).
XRD9827
17
Rev. 3.00
R
L
VRT
VRB
VDD
XRD9827
CLAMP
RINT
RED
M
U
X
C
I
S
REXT
CEXT
N/C
N/C
N/C
Therefore, Tc =1/R
INT
C
EXT
If the input to the external capacitor has a source
impedance (R
EXT
), then:
T
c
=1/(R
INT
+R
EXT
)C
EXT
This value corresponds to the black reference of the
image sensor. When the CLAMP pin is set back to low,
the ADC samples the video signal with respect to the
black reference. The typical value for the external
capacitor is 100pF. This value should be adjusted
according to the time constant (Tc) needed in a particu-
lar application. The CLAMP pin has an internal 150 ohm
impedance (R
INT
) which is in series with the external
capacitor (C
EXT
).
Figure 7. CIS AC Coupled Application
XRD9827
18
Rev. 3.00
DVDD (3V - 5V)
AVDD
VCC (5V - 15V)
DGND
AGND
DIGITAL
ASIC
C
I
S
N/C
N/C
N/C
100PF
0.1uF
0.1uF
0.01uF
0.1uF
0.01uF
XRD9827
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
Figure 8. Typical Application Circuitry CIS AC Coupled Non-Inverted

XRD9827ACU

Mfr. #:
Manufacturer:
MaxLinear
Description:
IC AFE 3 CHAN 12BIT 20SSOP
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New from this manufacturer.
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