OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

XRD9827ACU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
XRD9827
19
Rev. 3.00
CIS Mode Timing -- AC Coupled
(CLAMP enabled)
ADCCLK
tckhw
tcklw
tckpd
tap
tap
Pixel N-1 Pixel N
tdv
Pixel N+1
CIS
tdv
[5:0]
[11:6]
N-8
N-8
LSB
N-7
N-7
LSB
N-6
N-6
LSB
N-5 N-5
LSB
CLAMP
tclpw
MSB MSB MSB MSB
DB
Figure 9. Timing Diagram for Figure 8
ADCCLK Events
↓ ADC Sample & PGA Start Track of next Pixel
MSB Data Out
↑ LSB Data Out
HI ADC Track PGA Output
LO ADC Hold/Convert
Table 3.
CLAMP Events
HI PGA Tracks V
CLAMP
& C
EXT
is Charged to
V
BLACK
- V
CLAMP
, which is equal to V
BLACK
LO PGA Tracks VIN
PP
Table 4.
XRD9827
20
Rev. 3.00
Internal CIS Reference Circuit (DB 4 = 1)
The XRD9827 has an internal register reserved for
interfacing to the Canon CIS model number CVA-
60216K. When this register is selected, the VDCEXT
(Pin 16) becomes an output voltage of 1.24 volts. This
voltage can be directly connected to the VREF (Pin 5)
of the Canon sensor. This reduces the amount of
Figure 10. Typical Application Circuitry Internal CIS Reference Circuit Mode
CANON CIS Sensor, Model #CVA=60216k
components needed for biasing the Canon CIS sensor
(the external diodes and resistors typically used in this
application have been included inside the XRD9827 for
this mode of operation). Below is a typical application
circuit using the XRD9827 and the Canon CVA-60216K
CIS sensor.
AGND
DVDD (3V - 5V)
VCC (5V)
AVDD
DGND
AGND
DGND
DGND
DGND
DGND
DVDD (3V - 5V)
ASIC
DIGITAL
N/C
N/C
CANON CIS
SENSOR
0.1uF
0.01uF
0.1uF
0.01uF
0.1uF
XRD9827
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
CVA-60216K
VOUT
1
MODE
2
AGND
3
VCC
4
VREF
5
SP
6
CLK
7
LED COM
8
LED BLU
9
LED GRN
10
LED RED
11
FGND
12
10K
10K
10K
47uF
47uF
NPN
NPN
NPN
0.01uF
100uF
XRD9827
21
Rev. 3.00
Figure 11. Typical Application Circuitry Internal CIS Rotating Gain
and Offset Line-By-Line
CIS Line-By-Line Rotating Gain and Offset
(Configuration DB1 = 1, DB0 = 1)
Line-by-line rotating gain and offset minimizes the
amount of write cycles per scan. Pre-loaded values of
gain and offset can be loaded for each color before the
first line is scanned. Each gain and offset is cycled
AVDD
AGND
DGND
VCC (5V - 15V)
DVDD (3V - 5V)
ASIC
DIGITAL
C
I
S
N/C
0.01uF
0.1uF
0.1uF
0.1uF
XRD9827
DVDD
1
DB0
2
DB1
3
DB2
4
DB3
5
DB4
6
DB5/SCLK
7
DB6/SDATA
8
DB7/LD
9
DGND
10
ADCCLK
11
CLAMP
12
SYNCH
13
AGND
14
VREF+
15
VDCEXT
16
BLU
17
GRN
18
RED
19
AVDD
20
0.01uF
through line-by-line so that the gain and offset do not
have to be loaded in between lines. Below is the typical
application circuit and timing for this configuration.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

XRD9827ACU

Mfr. #:
Buy XRD9827ACU
Manufacturer:
MaxLinear
Description:
IC AFE 3 CHAN 12BIT 20SSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet