4-1734260-3 Datasheet 4-1734260-3, PXAG30KFA,529, PXAG30KFA,512 | P16-P18

Philips Semiconductors Product data

XA-G30

XA 16-bit microcontroller family

512 B RAM, watchdog, 2 UARTs

2002 Mar 25

PRE2 PRE1 PRE0 — — WDRUN WDTOF

WDCON

8–BIT DOWN

COUNTER

PRESCALERTCLK

MOV WFEED1,#A5H

MOV WFEED2,#5AH

WATCHDOG FEED SEQUENCE

WDL

SU00581A

—

INTERNAL RESET

Figure 10. Watchdog Timer in XA-G30

When the watchdog underflows, the following action takes place

(see Figure 10):

• Autoload takes place.

• Watchdog time-out flag is set

• Watchdog run bit unchanged.

• Autoload (WDL) register unchanged.

• Prescaler tap unchanged.

• All other device action same as external reset.

Note that if the watchdog underflows, the program counter will be

loaded from the reset vector as in the case of an internal reset. The

watchdog time-out flag can be examined to determine if the

watchdog has caused the reset condition. The watchdog time-out

flag bit can be cleared by software.

WDCON Register Bit Definitions

WDCON.7 PRE2 Prescaler Select 2, reset to 1

WDCON.6 PRE1 Prescaler Select 1, reset to 1

WDCON.5 PRE0 Prescaler Select 0, reset to 1

WDCON.4 —

WDCON.3 —

WDCON.2 WDRUN Watchdog Run Control bit, reset to 1

WDCON.1 WDTOF Timeout flag

WDCON.0 —

UARTs

The XA-G30 includes 2 UART ports that are compatible with the

enhanced UART used on the 8xC51FB. Baud rate selection is

somewhat different due to the clocking scheme used for the XA

timers.

Some other enhancements have been made to UART operation.

The first is that there are separate interrupt vectors for each UART’s

transmit and receive functions. The UART transmitter has been

double buffered, allowing packed transmission of data with no gaps

between bytes and less critical interrupt service routine timing. A

break detect function has been added to the UART. This operates

independently of the UART itself and provides a start-of-break status

bit that the program may test. Finally, an Overrun Error flag has

been added to detect missed characters in the received data

stream. The double buffered UART transmitter may require some

software changes in code written for the original XA-G30 single

buffered UART.

Each UART baud rate is determined by either a fixed division of the

oscillator (in UART modes 0 and 2) or by the timer 1 or timer 2

overflow rate (in UART modes 1 and 3).

Timer 1 defaults to clock both UART0 and UART1. Timer 2 can be

programmed to clock either UART0 through T2CON (via bits R0CLK

and T0CLK) or UART1 through T2MOD (via bits R1CLK and

T1CLK). In this case, the UART not clocked by T2 could use T1 as

the clock source.

The serial port receive and transmit registers are both accessed at

Special Function Register SnBUF. Writing to SnBUF loads the

transmit register, and reading SnBUF accesses a physically

separate receive register.

The serial port can operate in 4 modes:

Mode 0: Serial I/O expansion mode. Serial data enters and exits

through RxDn. TxDn outputs the shift clock. 8 bits are

transmitted/received (LSB first). (The baud rate is fixed at 1/16 the

oscillator frequency.)

Mode 1: Standard 8-bit UART mode. 10 bits are transmitted

(through TxDn) or received (through RxDn): a start bit (0), 8 data

bits (LSB first), and a stop bit (1). On receive, the stop bit goes into

RB8 in Special Function Register SnCON. The baud rate is variable.

Mode 2: Fixed rate 9-bit UART mode. 11 bits are transmitted

(through TxD) or received (through RxD): start bit (0), 8 data bits

(LSB first), a programmable 9th data bit, and a stop bit (1). On

Transmit, the 9th data bit (TB8_n in SnCON) can be assigned the

value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could

be moved into TB8_n. On receive, the 9th data bit goes into RB8_n

in Special Function Register SnCON, while the stop bit is ignored.

The baud rate is programmable to 1/32 of the oscillator frequency.

Mode 3: Standard 9-bit UART mode. 11 bits are transmitted

(through TxDn) or received (through RxDn): a start bit (0), 8 data

bits (LSB first), a programmable 9th data bit, and a stop bit (1).

In fact, Mode 3 is the same as Mode 2 in all respects except baud

rate. The baud rate in Mode 3 is variable.

In all four modes, transmission is initiated by any instruction that

uses SnBUF as a destination register. Reception is initiated in

Mode 0 by the condition RI_n = 0 and REN_n = 1. Reception is

initiated in the other modes by the incoming start bit if REN_n = 1.

Philips Semiconductors Product data

XA-G30

XA 16-bit microcontroller family

512 B RAM, watchdog, 2 UARTs

2002 Mar 25

Serial Port Control Register

The serial port control and status register is the Special Function

the mode selection bits, but also the 9th data bit for transmit and

receive (TB8_n and RB8_n), and the serial port interrupt bits (TI_n

and RI_n).

TI Flag

In order to allow easy use of the double buffered UART transmitter

feature, the TI_n flag is set by the UART hardware under two

conditions. The first condition is the completion of any byte

transmission. This occurs at the end of the stop bit in modes 1, 2, or

3, or at the end of the eighth data bit in mode 0. The second

condition is when SnBUF is written while the UART transmitter is

idle. In this case, the TI_n flag is set in order to indicate that the

second UART transmitter buffer is still available.

Typically, UART transmitters generate one interrupt per byte

transmitted. In the case of the XA UART, one additional interrupt is

generated as defined by the stated conditions for setting the TI_n

flag. This additional interrupt does not occur if double buffering is

bypassed as explained below. Note that if a character oriented

approach is used to transmit data through the UART, there could be

a second interrupt for each character transmitted, depending on the

timing of the writes to SBUF. For this reason, it is generally better to

bypass double buffering when the UART transmitter is used in

character oriented mode. This is also true if the UART is polled

rather than interrupt driven, and when transmission is character

oriented rather than message or string oriented. The interrupt occurs

at the end of the last byte transmitted when the UART becomes idle.

Among other things, this allows a program to determine when a

message has been transmitted completely. The interrupt service

routine should handle this additional interrupt.

The recommended method of using the double buffering in the

application program is to have the interrupt service routine handle a

single byte for each interrupt occurrence. In this manner the

program essentially does not require any special considerations for

double buffering. Unless higher priority interrupts cause delays in

the servicing of the UART transmitter interrupt, the double buffering

will result in transmitted bytes being tightly packed with no

intervening gaps.

9-bit Mode

Please note that the ninth data bit (TB8) is not double buffered. Care

must be taken to insure that the TB8 bit contains the intended data

at the point where it is transmitted. Double buffering of the UART

transmitter may be bypassed as a simple means of synchronizing

TB8 to the rest of the data stream.

Bypassing Double Buffering

The UART transmitter may be used as if it is single buffered. The

recommended UART transmitter interrupt service routine (ISR)

technique to bypass double buffering first clears the TI_n flag upon

entry into the ISR, as in standard practice. This clears the interrupt

that activated the ISR. Secondly, the TI_n flag is cleared

immediately following each write to SnBUF. This clears the interrupt

flag that would otherwise direct the program to write to the second

transmitter buffer. If there is any possibility that a higher priority

interrupt might become active between the write to SnBUF and the

clearing of the TI_n flag, the interrupt system may have to be

temporarily disabled during that sequence by clearing, then setting

the EA bit in the IEL register.

Note Regarding Older XA-G30 Devices

Older versions of the XA-G30, XA-G37, and XA-G35 emulation

bondout devices do not have the double buffering feature enabled.

Contact factory for details.

Philips Semiconductors Product data

XA-G30

XA 16-bit microcontroller family

512 B RAM, watchdog, 2 UARTs

2002 Mar 25

CLOCKING SCHEME/BAUD RATE GENERATION

The XA UARTS clock rates are determined by either a fixed division

(modes 0 and 2) of the oscillator clock or by the Timer 1 or Timer 2

overflow rate (modes 1 and 3).

The clock for the UARTs in XA runs at 16x the Baud rate. If the

timers are used as the source for Baud Clock, since maximum

speed of timers/Baud Clock is Osc/4, the maximum baud rate is

timer overflow divided by 16 i.e. Osc/64.

In Mode 0, it is fixed at Osc/16. In Mode 2, however, the fixed rate is

Osc/32.

00 Osc/4

Pre-scaler

for all Timers T0 1 2

01 Osc/16

or a

mers

controlled b

PT1

PT0

Osc/64

controlled

PT1,

PT0

bits in SCR

11 reserved

Baud Rate for UART Mode 0:

Baud_Rate = Osc/16

Baud Rate calculation for UART Mode 1 and 3:

Baud_Rate = Timer_Rate/16

Timer_Rate = Osc/(N*(Timer_Range– Timer_Reload_Value))

where N = the TCLK prescaler value: 4, 16, or 64.

and Timer_Range = 256 for timer 1 in mode 2.

65536 for timer 1 in mode 0 and timer 2

in count up mode.

The timer reload value may be calculated as follows:

Timer_Reload_Value = Timer_Range–(Osc/(Baud_Rate*N*16))

NOTES:

1. The maximum baud rate for a UART in mode 1 or 3 is Osc/64.

2. The lowest possible baud rate (for a given oscillator frequency

and N value) may be found by using a timer reload value of 0.

3. The timer reload value may never be larger than the timer range.

4. If a timer reload value calculation gives a negative or fractional

result, the baud rate requested is not possible at the given

oscillator frequency and N value.

Baud Rate for UART Mode 2:

Baud_Rate = Osc/32

Using Timer 2 to Generate Baud Rates

Timer T2 is a 16-bit up/down counter in XA. As a baud rate

generator, timer 2 is selected as a clock source for either/both

UART0 and UART1 transmitters and/or receivers by setting TCLKn

and/or RCLKn in T2CON and T2MOD. As the baud rate generator,

T2 is incremented as Osc/N where N = 4, 16 or 64 depending on

TCLK as programmed in the SCR bits PT1, and PTO. So, if T2 is

the source of one UART, the other UART could be clocked by either

T1 overflow or fixed clock, and the UARTs could run independently

with different baud rates.

T2CON

bit5 bit4

0x418

RCLK0 TCLK0

T2MOD

bit5 bit4

0x419

RCLK1 TCLK1

Prescaler Select for Timer Clock (TCLK)

SCR

bit3 bit2

0x440

PT1 PT0

STINTn

BIT SYMBOL FUNCTION

SnSTAT.3 FEn Framing Error flag is set when the receiver fails to see a valid STOP bit at the end of the frame.

Cleared by software.

SnSTAT.2 BRn Break Detect flag is set if a character is received with all bits (including STOP bit) being logic ‘0’. Thus

it gives a “Start of Break Detect” on bit 8 for Mode 1 and bit 9 for Modes 2 and 3. The break detect

feature operates independently of the UARTs and provides the START of Break Detect status bit that

a user program may poll. Cleared by software.

SnSTAT.1 OEn Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before

the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is

received while RI in SnCON is still set. Cleared by software.

SnSTAT.0 STINTn This flag must be set to enable any of the above status flags to generate a receive interrupt (RIn). The

only way it can be cleared is by a software write to this register.

SU00607B

OEnBRnFEn————

SnSTAT Address: S0STAT 421

S1STAT 425

Bit Addressable

Reset Value: 00H

LSBMSB

Figure 11. Serial Port Extended Status (SnSTAT) Register

(See also Figure 13 regarding Framing Error flag)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

4-1734260-3

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Buy 4-1734260-3

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