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4-1734260-3

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Philips Semiconductors Product data
XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
2002 Mar 25
20
INTERRUPTS
The XA-G30 supports 38 vectored interrupt sources. These include
9 maskable event interrupts, 7 exception interrupts, 16 trap
interrupts, and 7 software interrupts. The maskable interrupts each
have 8 priority levels and may be globally and/or individually enabled
or disabled.
The XA defines four types of interrupts:
• Exception Interrupts – These are system level errors and other
very important occurrences which include stack overflow,
divide-by-0, and reset.
• Event interrupts – These are peripheral interrupts from devices
such as UARTs, timers, and external interrupt inputs.
• Software Interrupts – These are equivalent of hardware
interrupt, but are requested only under software control.
• Trap Interrupts – These are TRAP instructions, generally used to
call system services in a multi-tasking system.
Exception interrupts, software interrupts, and trap interrupts are
generally standard for XA derivatives and are detailed in the
XA
User Guide
. Event interrupts tend to be different on different XA
derivatives.
The XA-G30 supports a total of 9 maskable event interrupt sources
(for the various XA peripherals), seven software interrupts, 5
exception interrupts (plus reset), and 16 traps. The maskable event
interrupts share a global interrupt disable bit (the EA bit in the IEL
register) and each also has a separate individual interrupt enable bit
(in the IEL or IEH registers). Only three bits of the IPA register
values are used on the XA-G30. Each event interrupt can be set to
occur at one of 8 priority levels via bits in the Interrupt Priority (IP)
registers, IPA0 through IPA5. The value 0 in the IPA field gives the
interrupt priority 0, in effect disabling the interrupt. A value of 1 gives
the interrupt a priority of 9, the value 2 gives priority 10, etc. The
result is the same as if all four bits were used and the top bit set for
all values except 0. Details of the priority scheme may be found in
the XA User Guide.
The complete interrupt vector list for the XA-G30, including all 4
interrupt types, is shown in the following tables. The tables include
the address of the vector for each interrupt, the related priority
register bits (if any), and the arbitration ranking for that interrupt
source. The arbitration ranking determines the order in which
interrupts are processed if more than one interrupt of the same
priority occurs simultaneously.
Table 5. Interrupt Vectors
EXCEPTION/TRAPS PRECEDENCE
DESCRIPTION VECTOR ADDRESS ARBITRATION RANKING
Reset (h/w, watchdog, s/w) 0000–0003 0 (High)
Breakpoint (h/w trap 1) 0004–0007 1
Trace (h/w trap 2) 0008–000B 1
Stack Overflow (h/w trap 3) 000C–000F 1
Divide by 0 (h/w trap 4) 0010–0013 1
User RETI (h/w trap 5) 0014–0017 1
TRAP 0– 15 (software) 0040–007F 1
EVENT INTERRUPTS
DESCRIPTION FLAG BIT
VECTOR
ADDRESS
ENABLE BIT INTERRUPT PRIORITY
ARBITRATION
RANKING
External interrupt 0 IE0 0080–0083 EX0 IPA0.2–0 (PX0) 2
Timer 0 interrupt TF0 0084–0087 ET0 IPA0.6–4 (PT0) 3
External interrupt 1 IE1 0088–008B EX1 IPA1.2–0 (PX1) 4
Timer 1 interrupt TF1 008C–008F ET1 IPA1.6–4 (PT1) 5
Timer 2 interrupt TF2(EXF2) 0090–0093 ET2 IPA2.2–0 (PT2) 6
Serial port 0 Rx RI.0 00A0–00A3 ERI0 IPA4.2–0 (PRIO) 7
Serial port 0 Tx TI.0 00A4–00A7 ETI0 IPA4.6–4 (PTIO) 8
Serial port 1 Rx RI.1 00A8–00AB ERI1 IPA5.2–0 (PRT1) 9
Serial port 1 Tx TI.1 00AC–00AF ETI1 IPA5.6–4 (PTI1) 10
SOFTWARE INTERRUPTS
DESCRIPTION FLAG BIT
VECTOR
ADDRESS
ENABLE BIT INTERRUPT PRIORITY
Software interrupt 1 SWR1 0100–0103 SWE1 (fixed at 1)
Software interrupt 2 SWR2 0104–0107 SWE2 (fixed at 2)
Software interrupt 3 SWR3 0108–010B SWE3 (fixed at 3)
Software interrupt 4 SWR4 010C–010F SWE4 (fixed at 4)
Software interrupt 5 SWR5 0110–0113 SWE5 (fixed at 5)
Software interrupt 6 SWR6 0114–0117 SWE6 (fixed at 6)
Software interrupt 7 SWR7 0118–011B SWE7 (fixed at 7)
Philips Semiconductors Product data
XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
2002 Mar 25
21
ABSOLUTE MAXIMUM RATINGS
PARAMETER RATING UNIT
Operating temperature under bias –55 to +125 °C
Storage temperature range –65 to +150 °C
Voltage on EA/V
PP
pin to V
SS
0 to +13.0 V
Voltage on any other pin to V
SS
–0.5 to V
DD
+0.5 V V
Maximum I
OL
per I/O pin 15 mA
Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W
DC ELECTRICAL CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V unless otherwise specified; V
DD
= T
amb
= 0 to 70 °C for commercial, –40 °C to +85 °C for industrial, unless otherwise
specified.
SYMBOL
PARAMETER
LIMITS
UNIT
SYMBOL
PARAMETER
MIN TYP MAX
UNIT
Supplies
I
DD
Supply current operating
9,10
f
osc
= 30 MHz,
T
amb
= 0 to 70 °C
– 30 40 mA
I
DD
Supply current operating
9,10
f
osc
= 30 MHz,
T
amb
= –40 to +85 °C
– 35 45 mA
I
ID
Idle mode supply current
9,10
f
osc
= 30 MHz – 22 30 mA
I
PD
Power-down current T
amb
= 0 to 70 °C – 15 100
mA
I
PD
Power-down current T
amb
= –40°C to +85°C – 150
mA
V
RAM
RAM-keep-alive voltage RAM-keep-alive voltage 1.5 – V
V
IL
Input low voltage – –0.5 0.22 V
DD
V
V
IH
In
p
ut high voltage exce
p
t XTAL1 RST
At 5.0 V 2.2 – V
V
IH
In ut
high
voltage
,
exce t
XTAL1
,
RST
At 3.3 V 2 – V
V
IH1
Input high voltage to XTAL1, RST For both 3.0 & 5.0 V 0.7 V
DD
– V
V
OL
Out
p
ut low voltage all
p
orts ALE PSEN
3
I
OL
= 3.2mA, V
DD
= 5.0 V – 0.5 V
V
OL
Out ut
low
voltage
all
orts
,
ALE
,
PSEN
3
1.0mA, V
DD
= 3.0 V – 0.4 V
V
OH1
Out
p
ut high voltage all
p
orts ALE PSEN
1
I
OH
= –100mA, V
DD
= 4.5 V
2.4 – V
V
OH1
Out ut
high
voltage
all
orts
,
ALE
,
PSEN
1
I
OH
= –15mA, V
DD
= 2.7 V
2.0 – V
V
OH2
Out
p
ut high voltage
p
orts P0–3 ALE PSEN
2
I
OH
= 3.2mA, V
DD
= 4.5 V 2.4 – V
V
OH2
Out ut
high
voltage
,
orts
P0
–
3
,
ALE
,
PSEN
2
I
OH
= 1mA, V
DD
= 2.7 V 2.2 – V
C
IO
Input/Output pin capacitance – – 15 pF
I
IL
Logical 0 input current, P0–3
6
V
IN
= 0.45 V – –25 –75
mA
I
LI
Input leakage current, P0–3
5
V
IN
= V
IL
or V
IH
– ±10
mA
I
TL
Logical 1 to 0 transition current all ports
4
At 5.5 V – –650
mA
NOTES:
1. Ports in Quasi bi-directional mode with weak pull-up (applies to ALE, PSEN
only during RESET).
2. Ports in Push-Pull mode, both pull-up and pull-down assumed to be same strength
3. In all output modes
4. Port pins source a transition current when used in quasi-bidirectional mode and externally driven from 1 to 0. This current is highest when
V
IN
is approximately 2 V.
5. Measured with port in high impedance output mode.
6. Measured with port in quasi-bidirectional output mode.
7. Load capacitance for all outputs=80 pF.
8. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
Maximum I
OL
per port pin: 15 mA (*NOTE: This is 85°C specification for V
DD
= 5 V.)
Maximum I
OL
per 8-bit port: 26 mA
Maximum total I
OL
for all output: 71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. See Figures 25, 26, 29, and 30 for I
DD
test conditions, and Figures 27 and 28 for I
CC
vs. Frequency.
Max. 5 V Active I
DD
= (fosc × 1.33 mA) + 5 mA
Max. 5 V Idle I
ID
= (fosc × 0.87 mA) + 4 mA
10.V
DDMIN
= 2.85 V operating at f
OSC
= 30 MHz and –40 °C to +85 °C
Philips Semiconductors Product data
XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
2002 Mar 25
22
AC ELECTRICAL CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; T
amb
= 0 to +70 °C for commercial, –40 °C to +85 °C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
SYMBOL
FIGURE
PARAMETER
MIN MAX
UNIT
External Clock
f
C
Oscillator frequency
All devices except PXAG30KFx
0
30 MHz
PXAG30KFx V
DD
= 2.85 V to 5.5 V 0 30 MHz
T
amb
= –40 °C to +85 °C V
DD
= 2.7 V to 2.85 V 0 25 MHz
t
C
22 Clock period and CPU timing cycle 1/f
C
ns
t
CHCX
22 Clock high time t
C
* 0.5 ns
t
CLCX
22 Clock low time t
C
* 0.4 ns
t
CLCH
22 Clock rise time 5 ns
t
CHCL
22 Clock fall time 5 ns
AC ELECTRICAL CHARACTERISTICS (V
DD
= 4.5 V TO 5.5 V)
T
amb
= 0 to +70 °C for commercial, –40 °C to +85 °C for industrial.
SYMBOL
FIGURE
PARAMETER
VARIABLE CLOCK
UNIT
SYMBOL
FIGURE
PARAMETER
MIN MAX
UNIT
Address Cycle
t
CRAR
21 Delay from clock rising edge to ALE rising edge 10 46 ns
t
LHLL
16 ALE pulse width (programmable) (V1 * t
C
) – 6 ns
t
AVLL
16 Address valid to ALE de-asserted (set-up) (V1 * t
C
) – 12 ns
t
LLAX
16 Address hold after ALE de-asserted (t
C
/2) – 10 ns
Code Read Cycle
t
PLPH
16 PSEN pulse width (V2 * t
C
) – 10 ns
t
LLPL
16 ALE de-asserted to PSEN asserted (t
C
/2) – 7 ns
t
AVIVA
16 Address valid to instruction valid, ALE cycle (access time) (V3 * t
C
) – 36 ns
t
AVIVB
17 Address valid to instruction valid, non-ALE cycle (access time) (V4 * t
C
) – 29 ns
t
PLIV
16 PSEN asserted to instruction valid (enable time) (V2 * t
C
) – 29 ns
t
PXIX
16 Instruction hold after PSEN de-asserted 0 ns
t
PXIZ
16 Bus 3-State after PSEN de-asserted (disable time) t
C
– 8 ns
t
IXUA
16 Hold time of unlatched part of address after instruction latched 0 ns
Data Read Cycle
t
RLRH
18 RD pulse width (V7 * t
C
) – 10 ns
t
LLRL
18 ALE de-asserted to RD asserted (t
C
/2) – 7 ns
t
AVDVA
18 Address valid to data input valid, ALE cycle (access time) (V6 * t
C
) – 36 ns
t
AVDVB
19 Address valid to data input valid, non-ALE cycle (access time) (V5 * t
C
) – 29 ns
t
RLDV
18 RD low to valid data in, enable time (V7 * t
C
) – 29 ns
t
RHDX
18 Data hold time after RD de-asserted 0 ns
t
RHDZ
18 Bus 3-State after RD de-asserted (disable time) t
C
– 8 ns
t
DXUA
18 Hold time of unlatched part of address after data latched 0 ns
Data Write Cycle
t
WLWH
20 WR pulse width (V8 * t
C
) – 10 ns
t
LLWL
20 ALE falling edge to WR asserted (V12 * t
C
) – 10 ns
t
QVWX
20 Data valid before WR asserted (data setup time) (V13 * t
C
) – 22 ns
t
WHQX
20 Data hold time after WR de-asserted (Note 6) (V11 * t
C
) – 5 ns
t
AVWL
20 Address valid to WR asserted (address setup time) (Note 5) (V9 * t
C
) – 22 ns
t
UAWH
20 Hold time of unlatched part of address after WR is de-asserted (V11 * t
C
) – 7 ns
Wait Input
t
WTH
21 WAIT stable after bus strobe (RD, WR, or PSEN) asserted (V10 * t
C
) – 30 ns
t
WTL
21 WAIT hold after bus strobe (RD, WR, or PSEN) assertion (V10 * t
C
) – 5 ns
NOTES ON PAGE 23.
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4-1734260-3

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