Philips Semiconductors Product data
XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
2002 Mar 25
26
ALE
MULTIPLEXED
ADDRESS
AND DATA
UNMULTIPLEXED
ADDRESS
RD
DATA IN *
A4–A11 or A4–A19
A0 or A1–A3, A12–A19
t
LLRL
t
RLRH
t
LLAX
t
AVLL
t
RHDX
t
RHDZ
t
AVDVA
t
RLDV
SU00947
t
DXUA
* DATA IN is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
Figure 18. External Data Memory Read Cycle (ALE Cycle)
ALE
MULTIPLEXED
ADDRESS
AND DATA
UNMULTIPLEXED
ADDRESS
RD
D0–D7
A4–A11
A0–A3, A12–A19
SU00708A
t
AVDVB
A0–A3, A12–A19
DATA IN
*
Figure 19. External Data Memory Read Cycle (Non-ALE Cycle) 8 Bit Bus Only
Philips Semiconductors Product data
XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
2002 Mar 25
27
t
UAWH
t
LLAX
ALE
MULTIPLEXED
ADDRESS
AND DATA
UNMULTIPLEXED
ADDRESS
WRL
or WRH
A4–A11 or A4–A15
DATA OUT
*
A0 or A1–A3, A12–A19
t
LLWL
t
WLWH
t
AVLL
t
AVWL
t
QVWX
t
WHQX
SU00584C
* DATA OUT is either D0–D7 or D0–D15, depending on the bus width (8 or 16 bits).
Figure 20. External Data Memory Write Cycle
XTAL1
ADDRESS BUS
WAIT
SU00709A
t
WTL
ALE
BUS STROBE
(WRL, WRH,
RD, OR PSEN)
t
WTH
t
CRAR
(The dashed line shows the strobe without WAIT.)
Figure 21. WAIT Signal Timing
Philips Semiconductors Product data
XA-G30
XA 16-bit microcontroller family
512 B RAM, watchdog, 2 UARTs
2002 Mar 25
28
V
DD
–0.5
0.45V
0.7V
DD
0.2V
DD
–0.1
t
CHCL
t
C
t
CLCH
t
CLCX
t
CHCX
SU00842
Figure 22. External Clock Drive
V
DD
–0.5
0.45V
0.2V
DD
+0.9
0.2V
DD
–0.1
NOTE:
AC inputs during testing are driven at V
DD
–0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at the 50% point of transitions.
SU00703A
Figure 23. AC Testing Input/Output
V
LOAD
V
LOAD
+0.1V
V
LOAD
–0.1V
V
OH
–0.1V
V
OL
+0.1V
NOTE:
TIMING
REFERENCE
POINTS
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded V
OH
/V
OL
level occurs. I
OH
/I
OL
±20mA.
SU00011
Figure 24. Float Waveform
V
DD
EA
RST
XTAL1
XTAL2
V
SS
V
DD
(NC)
CLOCK SIGNAL
SU00591B
Figure 25. I
DD
Test Condition, Active Mode
All other pins are disconnected
V
DD
EA
RST
XTAL1
XTAL2
V
SS
V
DD
(NC)
CLOCK SIGNAL
SU00590B
V
DD
Figure 26. I
DD
Test Condition, Idle Mode
All other pins are disconnected

4-1734260-3

Mfr. #:
Manufacturer:
TE Connectivity
Description:
Headers & Wire Housings WTB 1.25 PTH 30U GLD 13 POS
Lifecycle:
New from this manufacturer.
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