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KS8737-EVAL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
KS8737 Micrel
KS8737 4 August 2003
Table Of Contents
Pin Description ............................................................................................................................................................ 5
Pin Configuration ........................................................................................................................................................ 8
Functional Description................................................................................................................................................ 9
100BaseTX Transmit ............................................................................................................................................. 9
100BaseTX Receive .............................................................................................................................................. 9
PLL Clock Synthesizer........................................................................................................................................... 9
Scrambler/De-scrambler (100BaseTX only) .......................................................................................................... 9
10BaseT Transmit ................................................................................................................................................. 9
10BaseT Receive .................................................................................................................................................. 9
SQE and Jabber Function (10Base only) .............................................................................................................. 9
Auto-Negotiation .................................................................................................................................................. 10
MII Management Interface ................................................................................................................................... 10
MII Data Interface ................................................................................................................................................ 10
Transmit Clock ............................................................................................................................................. 10
Receive Clock .............................................................................................................................................. 10
Transmit Enable ........................................................................................................................................... 10
Receive Data Valid ...................................................................................................................................... 10
Error Signals ................................................................................................................................................ 11
Carrier Sense ............................................................................................................................................... 11
Collision ....................................................................................................................................................... 11
Power Management............................................................................................................................................. 11
Fiber Mode........................................................................................................................................................... 11
Media Converter Option....................................................................................................................................... 11
Register Map ........................................................................................................................................................... 12
Register 0h: Basic Conrol ................................................................................................................................... 12
Register 1h: Basic Status.................................................................................................................................... 12
Register 2h: PHY Identifier 1 .............................................................................................................................. 13
Register 3h: PHY Identifier 2 .............................................................................................................................. 13
Register 4h: Auto-Negotiation Advertisement ..................................................................................................... 13
Register 5h: Auto-Negotiation Link Partner Ability .............................................................................................. 14
Register 6h: Auto-Negotiation Expansion ........................................................................................................... 14
Register 7h: Auto-Negotiation Next Page ........................................................................................................... 14
Register 15h: RXER Counter .............................................................................................................................. 14
Register 1bh: Interrupt Control/Status Register .................................................................................................. 15
Register 1fh: 100BaseTX PHY Controller ........................................................................................................... 15
Mode Selection for Registers ................................................................................................................................... 17
Typical Application Circuit ....................................................................................................................................... 18
Absolute Maximum Ratings ..................................................................................................................................... 19
Operating Ratings ..................................................................................................................................................... 19
Electrical Characteristics.......................................................................................................................................... 19
Timing Diagrams ....................................................................................................................................................... 21
Selection of Isolation Transformers ........................................................................................................................ 27
Selection of Reference Crystals............................................................................................................................... 27
Package Outline and Dimensions............................................................................................................................ 28
August 2003 5 KS8737
KS8737 Micrel
Pin Description
Pin Number Pin Name Type
(Note 1)
Pin Function
1 CRS O MII Carrier Sense Output. Active High. High impedance when PHY is isolated.
2 INTRPT I/O Interrupt Output. This pin requires an external 10k pull-up resistor. This pin
becomes an I/O pin for factory testing in the test mode.
3 RXENB I/O MII Receive Enable Input. Active Low. If this pin is High, the Receive output of
MII (RXD[3:0], RXDV, RXER, RXC) will be in tri-state. This pin becomes an I/O
pin for factory testing in the test mode.
4 PHYAD4 I/O PHY Address Bit [4] Input. This pin becomes an I/O pin for factory testing in the
test mode.
5 PHYAD3 I/O PHY Address Bit [3] Input. This pin becomes an I/O pin for factory testing in the
test mode.
6 PHYAD2 I/O PHY Address Bit [2] Input. This pin becomes an I/O pin for factory testing in the
test mode.
7 PHYAD1 I/O PHY Address Bit [1] Input. This pin becomes an I/O pin for factory testing in the
test mode.
8 PHYAD0 I/O PHY Address Bit [0] Input. This pin becomes an I/O pin for factory testing in the
test mode.
9, 19, VDD P 3.3V power supply
24, 37, 53
10, 22, 26, GND GND Ground.
31, 43, 52, 63
11 X2 O Crystal Oscillator Output. This pin is connected to the other terminal of the
25MHz crystal. If X1 is driven by an external clock, X2 must be left open.
12 X1 I Crystal Oscillator Input. Input for a crystal or an external 25MHz clock.
13 FDX I/O Full-Duplex Input. If this pin is High, it sets full-duplex operation. If this pin is Low,
it sets half duplex operation. The input signal of this pin is latched at reset. After
reset, this pin becomes test pin for factory test.
14 MODE0 I/O Mode Select Input. These pins carry encoded input signals that are latched at
15 MODE1 reset and power up to set mode of operation. After reset, they become test pins
for factory test. These pins are I/O pins in the test mode.
16 RSTB* I Hardware Reset Input. Active Low signal. It forces the device to a known state.
Internal 100kΩ pull-up.
17,35, 36 NC No Connect.
33 DISTX/LPBK I Disable transmit Input. If this pin is high, it disables transmit only during the Media
converter mode. Floating is for normal operation. The DISTX/LPBK pin also
selects several functions together with the TST2 pin.
LPBK/DISTX TST2
High High Disable Transmit
High Float Local Loopback
Low High Remote Loopback
Low Float Remote Loopback
18 FXSD I Fiber Signal Detect. To detect fiber signal. Left open when not in use.
20 PWRSAVE/ I Power Saving Mode Initialization Input. (Affecting Register 1f.15). To disable
FXSD_THD power saving mode, tie this pin low; otherwise, power saving mode is asserted.
This pin can also be used to set FX signal detect threshold in fiber mode.
Note 1. P = power supply
G = ground
I = input
O = output
I/O = bi-directional
KS8737 Micrel
KS8737 6 August 2003
Pin Number Pin Name Type
(Note 1)
Pin Function
21 TXP O Twisted Pair Transmit Outputs. Differential transmit outputs for 100BaseTX
23 TXM or 10BaseT to magnetic.
25 ISET O Transmit Current Set. Connecting an external reference resistor to set transmitter
output current. This pin connected to a 22.1kΩ 1% resistor to ground if a
transformer of 1:1 turns ratio is used.
27 FIBIP I Fiber Receive Inputs. Differential pseudo-ECL receive pairs compatible with
28 FIBIM standard fiber transceiver for 100BaseFX. Both pins should be tied to ground if
not used or if not in the FX mode.
29 RXP I Twisted Pair Receive Input. Differential receive input pins for 100BaseTX or
30 RXM 10BaseT from the magnetics.
32 TST2 I Test Pin. During normal operation this pin should be left open. When tied high
through a 1k resistor the chip will operate in back to back TX to FX mode. In this
case, TXC becomes an input pin.
34 PWRDWN I Power Down Select Input. When this pin is tied high, the chip is in power down
mode. When this pin is open or tied low, the chip is in normal operation..
38 LEDSPD I/O LED Output. During normal operation, this pin lights the SPEED LED to indicate
100Mbps is selected. This pin becomes an I/O pin for factory testing in the test
mode. Active Low.
39 LEDCOL I/O LED Output. During normal operation, this pin lights the COL LED to indicate a
collision. It will flash at a rate of 50ms high and 50ms low when active. This pin
becomes an I/O pin for factory testing in the test mode. Active Low.
40 LEDLINK I/O LED Output. During normal operation, this pin lights the LINK LED to indicate a
good link is detected. This pin becomes an I/O pin for factory testing in the test
mode. Active Low.
41 LEDACT I/O LED Output. During normal operation, this pin lights the Activity LED when
transmitting or receiving. It will flash at a rate of 50ms high and 50ms low when
active. This pin becomes an I/O pin for factory testing in the test mode. Active
Low.
42 LEDFDX I/O LED Output. During normal operation, this pin lights the FDX LED to indicate a
full-duplex mode. This pin becomes an I/O pin for factory testing in the test mode.
Active Low.
44 MDIO I/O Serial Management Data Input/Output. This pin requires an external 10k pull-up
resistor.
45 MDC I Serial Management Interface Clock Input. This pin is synchronous to the MDIO
data interface.
46 FXMODEB I FX Mode Select Input. Active Low. When this pin is low, the KS8737 is in the
100BaseFX mode.
47 RXD3 O MII Receive Data Output. Active High, clocked out on the falling edge of RXCLK.
48 RXD2 RXD0 is the LSB. High impedance when PHY is isolated or if RXEN is de-
49 RXD1 asserted.
50 RXD0
51 RXDV/ O MII Receive Data Valid Output. Active High, clocked out on the falling edge of
CRSDV RXCLK. This signal indicates that recovered and decoded data nibbles are being
presented synchronously to RXCLK. High impedance when PHY is isolated or if
RXEN is de-asserted.
54 RXC O MII Receive Clock Output. 25MHz in 100BaseTX mode, 2.5MHz in 10BaseT
nibble mode. High impedance when PHY is isolated or if RXEN is de-asserted.
Note 1. P = power supply
G = ground
I = input
O = output
I/O = bi-directional
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

KS8737-EVAL

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