August 2003 9 KS8737
KS8737 Micrel
Functional Description
100BaseTX Transmit
The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and
transmission. The circuit starts with a parallel to serial conversion, which converts the 25 MHz, 4-bit nibbles into a 125 MHz
serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted
from NRZ to NRZI format, then transmitted in MLT3 current output. The output current is set by an external 1% 22.1kΩ resistor
for the 1: 1 transformer ratio. It has a typical rise/fall times of 4 ns and is complied to the ANSI TP-PMD standard regarding
amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output driver is also incorporated into the
100BaseTX driver, and the total output capacitance is typical 7pF with short PC board traces assumed.
100BaseTX Receive
The 100BaseTX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock
recovery, NRZI to NRZ conversion, and serial to parallel conversion. The receiving side starts with the equalization filter to
compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion is a
function of the length of the cable, the equalizer has to adjust its characteristic to optimize the performance. In this design, the
variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable
characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental
changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the
MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to
convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized
25MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at
the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both
TXC and RXC clocks continue to run.
PLL Clock Synthesizer
The KS8737 generates 125MHz, 25MHz and 20MHz clocks for system timing. An internal crystal oscillator circuit provides the
reference clock for the synthesizer.
Scrambler/De-scrambler (100BaseTX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander. The
KS8737 provides a scrambler-bypass mode for testing purpose. Bypassing the scrambler causes the PCS-layer encoder to
be bypassed such that the MII is operated in the 5B mode.
10BaseT Transmit
When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8737 will continue to encode and
transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition occurs
at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver is
incorporated into the 100Base driver to allow transmission with the same magnetic. They are internally wave-shaped and pre-
emphasized into outputs with typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental when
driven by an all-ones Manchester-encoded signal.
10BaseT Receive
On the receive side, input buffer and level detecting squelch circuit are employed. A differential input receiver circuit and a PLL
performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch
circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noises at the RXP or RXM input
from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the
KS8737 decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive data (RXD)
available. The receive clock is maintained active during idle periods in between data reception. The KS8737 supports extended
length cables for 10BaseT by selecting a lower squelch level around 150mV.
SQE and Jabber Function (10BaseT only)
In 10BaseT operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test
of the 10BaseT transmit/receive path and is called SQE test. The 10BaseT transmitter will be disabled and COL will go High
if TXEN is High for more than 46 us (Jabbering) If TXEN then goes Low for more than 368 us, the 10BaseT transmitter will
be re-enabled and COL will go Low.
