Data Sheet AD7796/AD7797
Rev. B | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AV
DD
to GND −0.3 V to +7 V
DV
DD
to GND −0.3 V to +7 V
Analog Input Voltage to GND −0.3 V to AV
DD
+ 0.3 V
Reference Input Voltage to GND −0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to GND −0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to GND −0.3 V to DV
DD
+ 0.3 V
AIN/Digital Input Current
10 mA
Operating Temperature Range 40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec)
220°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4.
Package Type θ
JA
θ
JC
Unit
TSSOP 128 14 °C/W
ESD CAUTION
AD7796/AD7797 Data Sheet
Rev. B | Page 8 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
1
2
3
4
5
6
7
8
CLK
CS
NC
NC
AIN(–)
AIN(+)
SCLK
NC
16
15
14
13
12
11
10
9
DOUT/RDY
DV
DD
AV
DD
REFIN(–)
REFIN(+)
NC
GND
DIN
TOP VIEW
(Not to Scale)
AD7796/
AD7797
06083-005
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 SCLK
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitt-
triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous
with all data transmitted in a constant train of pulses. Alternatively, it can be a noncontinuous clock with the
information being transmitted to or from the ADC in smaller batches of data.
2 CLK
Clock In/Clock Out. The internal clock can be made available at this pin. Alternatively, the internal clock can be
disabled, and the ADC can be driven by an external clock. This allows several ADCs to be driven from a
common clock, allowing simultaneous conversions to be performed.
3
CS
Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in
systems with more than one device on the serial bus or as a frame synchronization signal in communicating
with the device. CS
can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and
DOUT used to interface with the device.
4 NC No Connect.
5 AIN(+) Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−).
6 AIN(−) Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−).
7 NC No Connect.
8 NC No Connect.
9 REFIN(+)
Positive Reference Input/Analog Input. An external reference can be applied between REFIN(+) and REFIN(–).
REFIN(+) can lie anywhere between AV
DD
and GND + 0.1 V. The nominal reference voltage (REFIN(+) – REFIN(−))
is 2.5 V, but the devices function with a reference of 0.1 V to AV
DD
.
10 REFIN(−)
Negative Reference Input/Analog Input. REFIN(−) is the negative reference input for REFIN. This reference input
can lie anywhere between GND and AV
DD
− 0.1 V.
11 NC No Connect.
12 GND Ground Reference Point.
13 AV
DD
Supply Voltage, 2.7 V to 5.25 V.
14 DV
DD
Digital Interface Supply Voltage. The logic levels for the serial interface pins are related to this supply, which is
between 2.7 V and 5.25 V. The DV
DD
voltage is independent of the voltage on AV
DD
; therefore, AV
DD
can equal 5
V with DV
DD
at 3 V or vice versa.
15
DOUT/RDY
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output
pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-
chip data or control registers. In addition, DOUT/RDY
operates as a data ready pin, going low to indicate the
completion of a conversion. If the data is not read after the conversion, the pin goes high before the next
update occurs.
The DOUT/RDY
falling edge can be used as an interrupt to a processor, indicating that valid data is available.
With an external serial clock, the data can be read using the DOUT/RDY
pin. With CS low, the data/control word
information is placed on the DOUT/RDY
pin on the SCLK falling edge and is valid on the SCLK rising edge.
16 DIN
Serial Data Input. This serial data input accesses the input shift register on the ADC. Data in this shift register is
transferred to the control registers within the ADC; the register selection bits of the communication register
identify the appropriate register.
Data Sheet AD7796/AD7797
Rev. B | Page 9 of 24
RMS NOISE AND RESOLUTION SPECIFICATIONS
Table 6 shows the rms noise of the AD7796/AD7797 for some
of the update rates. The numbers given are for the bipolar input
range with an external 2.5 V reference. These numbers are typical
and are generated with a differential input voltage of 0 V. Table 7
and Table 8 show the effective resolution, while the output
peak-to-peak (p-p) resolution is shown in parentheses. It is
important to note that the effective resolution is calculated using
the rms noise, while the p-p resolution is based on the p-p
noise. The p-p resolution represents the resolution for which
there is no code flicker. These numbers are typical and are
rounded to the nearest 0.5 LSB.
Table 6. RMS Noise (µV) vs. Output Update Rate for the
AD7796/AD7797 Using a 2.5 V Reference
Update Rate (Hz) RMS Noise (µV)
4.17 0.065
6.25 0.07
8.33 0.08
10 0.09
12.5
0.1
16.7 0.12
33.2 0.17
50 0.21
62 0.23
123
0.43
Table 7. Typical Resolution (Bits) vs. Output Update Rate for
the AD7797 Using a 2.5 V Reference
Update Rate (Hz) Effective Bits (p-p)
4.17 19 (16.5)
6.25 19 (16.5)
8.33 19 (16)
10 18.5 (16)
12.5
18.5 (16)
16.7 18.5 (15.5)
33.2 18 (15)
50 17.5 (15)
62 17.5 (14.5)
123 16.5 (13.5)
Table 8. Typical Resolution (Bits) vs. Output Update Rate for
the AD7796 Using a 2.5 V Reference
Update Rate (Hz) Effective Bits (p-p)
4.17 16 (16)
6.25 16 (16)
8.33 16 (16)
10
16 (16)
12.5 16 (16)
16.7 16 (15.5)
33.2 16 (15)
50 16 (15)
62 16 (14.5)
123 16 (13.5)

AD7796BRUZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Low Power 16-Bit
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