DATA SHEET
ICS841664AGI REVISION A JULY 15, 2013 1 ©2013 Integrated Device Technology, Inc.
FemtoClock
®
Crystal-to-HCSL
Clock Generator
ICS841664I
0
1
1
0
÷
÷NA
÷NB
OSC
FemtoClock
PLL
VCO = 625MHz
M = 25
fref
XTAL_IN
25MHz
XTAL_OUT
REF_IN
REF_SEL
IREF
BYPASS
FSEL[0:1]
MR/nOE
nREF_OE
QB0
nQB0
QB1
nQB1
QA0
nQA0
QA1
nQA1
REF_OUT
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
1
2
3
4
5
6
7
nREF_OE
REF_OUT
GND
BYPASS
8
9
10
11
12
13
14
QA
V
DDA
V
DD
nQA
GND
QA
REF_IN
V
DDOA
REF_SEL
XTAL_IN
XTAL_OUT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
IREF
FSEL
QB
GND
MR/nOE
FSEL
nQB
V
DDOB
V
DD
GND
1
nQA1
QB1
nQB1
00
00
0
1
General Description
The ICS841664I is an optimized sRIO clock generator and a
member of the family of high-performance clock solutions from IDT.
The device uses a 25MHz parallel crystal to generate 125MHz and
156.25MHz clock signals, replacing solution requiring multiple
oscillator and fanout buffer solutions. The device has excellent phase
jitter (<1ps RMS) suitable to clock components requiring precise and
low-jitter sRIO clock signals. Designed for telecom, networking and
industrial application, the ICS841664I can also drive the high-speed
sRIO SerDes clock inputs of communication processors, DSPs,
switches and bridges.
Features
Four differential HCSL clock outputs: configurable for sRIO
(125MHz or 156.25MHz) clock signals
One REF_OUT LVCMOS/LVTTL clock output
Selectable crystal oscillator interface, 25MHz, 18pF parallel
resonant crystal or LVCMOS/LVTTL single-ended reference clock
input or LVCMOS/LVTTL single-ended input
Supports the following output frequencies: 125MHz or 156.25MHz
VCO: 625MHz
Supports PLL bypass and output enable functions
RMS phase jitter, using a 25MHz crystal (1.875MHz - 20MHz):
0.45ps (typical) @ 125MHz
Full 3.3V power supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
ICS841664I
28-Lead TSSOP
6.1mm x 9.7mm x 0.925mm
package body
G Package
Top View
Pin Assignment
Block Diagram
ICS841664AGI REVISION A JULY 15, 2013 2 ©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 18 V
DD
Power Core supply pins.
2 REF_OUT Output LVCMOS/LVTTL reference frequency clock output.
3, 7, 15, 22 GND Power Power supply ground.
4, 5,
8, 9
QA0, nQA0
QA1, nQA1
Output Differential Bank A output pairs. HCSL interface levels.
6V
DDOA
Power Output supply pin for Bank A outputs.
10 nREF_OE Input Pullup
Active low REF_OUT enable/disable. See Table 3E.
LVCMOS/LVTTL interface levels.
11 BYPASS Input Pulldown Selects PLL/PLL bypass mode. See Table 3C. LVCMOS/LVTTL interface levels.
12 REF_IN Input Pulldown LVCMOS/LVTTL reference clock input.
13 REF_SEL Input Pulldown
Reference select, Selects the input reference source. See Table 3B.
LVCMOS/LVTTL interface levels
14 V
DDA
Power Analog supply pin.
16,
17
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
19 MR/nOE Input Pulldown
Active HIGH master reset. Active LOW output enable. When logic HIGH, the
internal dividers are reset and the outputs are in high impedance. When logic
LOW, the internal dividers and the outputs are enabled. See Table 3D.
LVCMOS/LVTTL interface levels.
20, 21,
24, 25
nQB1, QB1
nQB0, QB0
Output Differential Bank B output pairs. HCSL interface levels.
23 V
DDOB
Power Output supply pin for Bank B outputs.
26,
27
FSEL1,
FSEL0
Input Pulldown Output frequency select pins. LVCMOS/LVTTL interface levels.
28 IREF Output
HCSL current reference resistor output. A fixed precision resistor (475) form this
pin to ground provides a reference current used for differential current-mode
QX[0:1], nQX[0:1] clock outputs.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4pF
C
PD
Power Dissipation Capacitance V
DD
= 3.465V 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output Impedance REF_OUT V
DD
= 3.465V 20
ICS841664AGI REVISION A JULY 15, 2013 3 ©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Function Tables
Table 3A. NA, NB FSELx Function Table (f
ref
= 25MHz)
Table 3B. REF_SEL Function Table
Table 3C. BYPASS Function Table
NOTE 1: Asynchronous control.
Table 3D. MR/nOE Function Table
NOTE 1: Asynchronous control.
Table 3E. nREF_OE Function Table
NOTE 1: Asynchronous control.
Inputs Outputs Frequency Settings
FSEL1 FSEL0 M QA[0:1], nQA[0:1] QB[0:1], nQB[0:1]
0 0 25 VCO/5 (125MHz) VCO/5 (125MHz)
0 1 25 VCO/5 (125MHz) VCO/4 (156.25MHz)
1 0 25 VCO/5 (125MHz) QB0:1 = L, nQB0:1 = H
1 1 25 VCO/4 (156.25MHz) VCO/4 (156.25MHz)
Input
REF_SEL Input Reference
0XTAL
1REF_IN
Input
BYPASS PLL Configuration
NOTE 1
0 PLL enabled
1 PLL bypassed (QA, QB = fref/Nx, x = A or B)
Input
MR/nOE Function
NOTE 1
0 Outputs enabled
1 Internal dividers reset, outputs disabled (High impedance)
Input
nREF_OE Function
NOTE 1
0 REF_OUT enabled
1 REF_OUT disabled (high impedance)

841664AGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 4 HCSL OUT SYNTHESIZER
Lifecycle:
New from this manufacturer.
Delivery:
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