ICS841664AGI REVISION A JULY 15, 2013 11 ©2013 Integrated Device Technology, Inc.
ICS841664I Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-HCSL CLOCK GENERATOR
Schematic Layout
Figure 1 shows an example of ICS841664I application schematic. In
this example, the device is operated at V
DD
= V
DDA
= V
DDOA
=
V
DDOB
= 3.3V. The 18pF parallel resonant 25MHz crystal is used.
The load capacitance C1 = 27pF and C2 = 27pF are recommended
for frequency accuracy. Depending on the parasitic of the printed
circuit board layout, these values might require a slight adjustment to
optimize the frequency accuracy. Crystals with other load
capacitance specifications can be used. This will require
adjusting C1 and C2. For this device, the crystal load capacitors are
required for proper operation.
As with any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS841664I provides
separate power supplies to isolate any high switching noise from
coupling into the internal PLL.
Figure 1. ICS841664I Schematic Example
In order to achieve the best possible filtering, it is recommended that
the placement of the filter components be on the device side of the
PCB as close to the power pins as possible. If space is limited, the
0.1µF capacitor in each power pin filter should be placed on the
device side of the PCB and the other components can be placed on
the opposite side.
Power supply filter recommendations are a general guideline to be
used for reducing external noise from coupling into the devices. The
filter performance is designed for wide range of noise frequency. This
low-pass filter starts to attenuate noise at approximately 10kHz. If a
specific frequency noise component with high amplitude interference
is known, such as switching power supplies frequencies, it is
recommended that component values be adjusted and if required,
additional filtering be added. Additionally general design practice for
power plane voltage stability suggests adding bulk capacitances in
the general area of all devices.
The schematic example focuses on functional connections and is not
configuration specific. Refer to the pin description and functional
tables in the datasheet to ensure the logic control inputs are properly
set.
VD D
REF _I N
Zo = 50
HCSL Termination
FSEL1
C12
0.1uF
RE F_O U T
VDDA
MR/nOE
R3 33
VDD
nQB1
R5
50
Zo = 50
Set Logic
Input to
'0'
nQ B0
VD D
R4 33
VDDOB=3. 3V
QB1
R1 0
50
+
-
nREF_OE
RU 2
Not Install
R8 0-33
C10
10uF
Zo = 50 Ohm
VDDOA=3. 3V
HCSL Optional
Termination
RD 2
1K
Zo = 50
Ro ~ 7 O hm
Q1
Driver_LVCMOS
Logic Control Input Examples
BLM18BB221SN2
Ferrite Bead
1 2
C1
27 p F
C8
0.1uF
(U 1 :6 )
R9 0-33
R6
50
C11
0. 1u F
Zo = 50
(U1:23)
VD D
FSEL0
VDDO
C7
0. 1 uF
C9
0.1uF
3. 3 V
R1 33
+
-
Optional
Set Logic
Input to
'1'
3. 3 V
To L ogi c
Input
pins
X1
25MHz
BLM18BB221SN1
Ferrite Bead
1 2
VDD
C4
10 u
R11
50
VDD=3. 3V
To Logic
Input
pins
R12
43
R7
10
LVCMOS
C3
0.1u
REF_SEL
Recommended for PCI
Express Point-to-Point
Connection
Zo = 50
C6
10uF
VD D
(U1:18)
RD 1
Not Install
VDDO
U1
1
2
3
4
5
14
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
12
13
28
27
26
25
VDD
REF _O U T
GN D
QA0
nQ A0
VDD A
VDD OA
GN D
QA1
nQ A1
nR E F _ O E
BYP ASS
GN D
XTAL_OUT
XT A L _ I N
VD D
MR/nOE
nQB1
QB1
GN D
VDDOB
nQB0
REF _I N
REF _SE L
IREF
FSEL0
FSEL1
QB0
C2
27pF
R2
47 5
(U 1 :1 )
VDD
C5
0.1uF
Recommended for PCI
Express Add-In Card
RU 1
1K
BY PA SS
VDDO
QB 0
