UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 28 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
8. Thermal characteristics
Layout conditions for R
th(j-a)
measurements: board finish thickness 1.6 mm ±10 %, board double
layer, board dimensions 129 mm × 60 mm, board material FR4, Cu thickness 0.070 mm, thermal
via separation 1.2 mm, thermal via diameter 0.3 mm ±0.08 mm, Cu thickness on vias 0.025 mm.
Optional heat sink top layer of 3.5 mm × 25 mm will reduce thermal resistance (see Figure 14
).
Fig 13. HTSSOP PCB
PCB copper area:
(bottom layer)
2 cm
2
PCB copper area:
(bottom layer)
8 cm
2
015aaa137
optional heatsink top layer
optional heatsink top layer
optional heatsink top layer
UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 29 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
[1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board.
[2] According to JEDEC JESD51-2, JESD51-5 and JESD51-7 at natural convection on 2s2p board. Board with
two inner copper layers (thickness: 35 μm) and thermal via array under the exposed pad connected to the
first inner copper layer.
Fig 14. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper
area
Table 9. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from junction to
ambient
single-layer board
[1]
78 K/W
four-layer board
[2]
36 K/W
PCB Cu heatsink area (cm
2
)
0 108462
015aaa138
50
70
90
R
th(j-a)
(K/W)
30
without heatsink top layer
with heatsink top layer
UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 30 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
9. Static characteristics
Table 10. Static characteristics
T
vj
=
40
°
C to +150
°
C; V
BAT
= 4.5 V to 28 V; V
BAT
> V
V1
; R
LIN
=500
Ω
; all voltages are defined with respect to ground;
positive currents flow in the IC; typical values are given at V
BAT
= 14 V; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply; pin BAT
V
BAT
battery supply voltage 4.5 - 28 V
I
BAT
battery supply current MC = 00 (Standby; V1 on)
STBCL = 1 (LIN wake-up enabled)
WIC1 = WIC2 = 11 (WAKE interrupts
enabled); 7.5 V < V
BAT
<28V
I
V1
=0mA; V
RSTN
= V
SCSN
= V
V1
V
TXDL
= V
V1
; V
SDI
=V
SCK
=0V
T
vj
= 40 °C-7589μA
T
vj
=25°C-6880μA
T
vj
=150°C-6273μA
MC = 01 (Sleep; V1 off)
STBCL = 1 (LIN wake-up enabled)
WIC1 = WIC2 = 11 (WAKE interrupts
enabled); 7.5 V < V
BAT
<28V
V
V1
=0V
T
vj
= 40 °C-5362μA
T
vj
=25°C-4957μA
T
vj
=150°C-4551μA
contributed by LIN wake-up receiver
STBCL = 1
V
LIN
=V
BAT
; 5.5 V < V
BAT
<28V
-1.12 μA
contributed by WAKEx pin edge
detectors; WIC1 = WIC2 = 11
V
WAKE1
=V
WAKE2
=V
BAT
0510μA
I
BAT(add)
additional battery supply
current
5.1 V < V
BAT
<7.5V - - 50 μA
4.5 V < V
BAT
<5.1V
V1 on (5 V version)
--3 mA
LIN Active mode (recessive)
STBCL = 0; MC = 1x
V
TXDL
= V
V1
; I
DLIN
=I
LIN
= 0 mA
5.5 V < V
BAT
<28V
- - 1300 μA
LIN Active mode (dominant)
STBCL = 0; MC = 1x
V
TXDL
= 0 V; I
DLIN
=I
LIN
= 0 mA
V
BAT
=14V
--5 mA
LIN Active mode (dominant)
STBCL = 0; MC = 1x
V
TXDL
= 0 V; I
DLIN
=I
LIN
= 0 mA
V
BAT
=28V
--10mA
V
th(det)pon
power-on detection threshold
voltage
4.5 - 5.5 V
V
th(det)poff
power-off detection threshold
voltage
4.25 - 4.5 V

UJA1079ATW/5V0WD,1

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC Hi Spd CAN Transcvr 4.5V-28V 6us
Lifecycle:
New from this manufacturer.
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