UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 37 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
[3] .
[4] t
PD(RX)sym
=t
PD(RX)r
− t
PD(RX)f
.
[5] A system reset will be performed if the watchdog is in Window mode and is triggered less than t
trig(wd)1
after the start of the watchdog
period (or in the first half of the watchdog period).
[6] The nominal watchdog period is programmed via the NWP control bits in the WD_and_Status register (see Table 4
); valid in watchdog
Window mode only.
[7] The watchdog will be reset if it is in window mode and is triggered at least t
trig(wd)1
, but not more than t
trig(wd)2
, after the start of the
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
δ2 δ4,
t
bus rec()max()
2t
bit
×
--------------------------------
=
Fig 15. Timing test circuit for LIN transceiver
SBC
BAT
DLIN
TXDL
R
LIN
C
LIN
RXDL
C
RXDL
LIN
GND
015aaa20
Fig 16. LIN transceiver timing diagram
015aaa133
V
TXDL
LIN bus signal
V
BAT
t
bit
t
bus(rec)(min)
V
th(rec)RX(max)
thresholds of
receiving node A
V
th(dom)RX(max)
V
th(rec)RX(min)
V
th(dom)RX(min)
t
PD(RX)r
t
PD(RX)f
t
PD(RX)r
t
PD(RX)f
t
bus(rec)(max)
t
bit
t
bit
thresholds of
receiving node B
output of receiving
node A
V
RXDL
output of receiving
node B
V
RXDL
t
bus(dom)(max)
t
bus(dom)(min)
