UJA1079A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 31 January 2011 6 of 46
NXP Semiconductors
UJA1079A
LIN core system basis chip
The exposed die pad at the bottom of the package allows for better heat dissipation from
the SBC via the printed-circuit board. The exposed die pad is not connected to any active
part of the IC and can be left floating, or can be connected to GND.
6. Functional description
The UJA1079A combines the functionality of a LIN transceiver, a voltage regulator and a
watchdog (UJA1079A/xx/WD versions) in a single, dedicated chip. It handles the
power-up and power-down functionality of the ECU and ensures advanced system
reliability. The SBC offers wake-up by bus activity, by cyclic wake-up and by the activation
of external switches. Additionally, it provides a periodic control signal for pulsed testing of
wake-up switches, allowing low-current operation even when the wake-up switches are
closed in Standby mode.
The LIN transceiver is optimized to be highly flexible with regard to bus topologies.
V1, the voltage regulator, is designed to power the ECU's microcontroller, its peripherals
and additional external transceivers. An external PNP transistor can be added to improve
heat distribution. The watchdog is clocked directly by the on-chip oscillator and can be
operated in Window, Timeout and Off modes.
6.1 System Controller
6.1.1 Introduction
The system controller manages register configuration and controls the internal functions
of the SBC. Detailed device status information is collected and presented to the
microcontroller. The system controller also provides the reset and interrupt signals.
WAKE1 18 local wake-up input 1
WAKE2 19 local wake-up input 2
i.c. 20 internally connected; should be left floating
i.c. 21 internally connected; should be left floating
i.c. 22 internally connected; should be left floating
GND 23 ground
i.c. 24 internally connected; should be left floating
LIN 25 LIN bus line
DLIN 26 LIN termination resistor connection
i.c. 27 internally connected; should be left floating
WBIAS 28 control pin for external wake biasing transistor
VEXCC 29 current measurement for external PNP transistor; this pin is connected to
the collector of the external PNP transistor
TEST2 30 test pin; pin should be connected to ground
VEXCTRL 31 control pin of the external PNP transistor; this pin is connected to the base
of the external PNP transistor
BAT 32 battery supply for the SBC
Table 2. Pin description
…continued
Symbol Pin Description
